NPIC6C596A_15 Datasheet, PDF (1/21 Pages) NXP Semiconductors – Power logic 8-bit shift register open-drain outputs

NPIC6C596A
Power logic 8-bit shift register; open-drain outputs
Rev. 1 — 23 October 2013
Product data sheet
1. General description
The NPIC6C596A is an 8-bit serial-in/serial or parallel-out shift register with a storage
register and open-drain outputs. Both the shift and storage register have separate clocks.
The device features a serial input (DS) and a serial output (Q7S) to enable cascading and
an asynchronous reset MR input. A LOW on MR resets both the shift register and storage
register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in
the shift register is transferred to the storage register on a LOW-to-HIGH transition of the
STCP input. If both clocks are connected together, the shift register is always one clock
pulse ahead of the storage register. To provide additional hold time in cascaded
applications, the serial output QS7 is clocked out on the falling edge of SHCP. Data in the
storage register drives the gate of the output extended-drain NMOS (EDNMOS) transistor
whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to
assume a high-impedance OFF-state. Operation of the OE input does not affect the state
of the registers.
The open-drain outputs are 33 V/100 mA continuous current extended-drain NMOS
transistors designed for use in systems that require moderate load power such as LEDs.
Integrated voltage clamps in the outputs provide protection against inductive transients.
These voltage clamps make the device suitable for power driver applications such as
relays, solenoids and other low-current or medium-voltage loads.
2. Features and benefits
 Specified from 40 C to +125 C
 Wide supply range 2.3 V to 5.5 V
 Low R_DSon
 Eight Power EDNMOS transistor outputs of 100 mA continuous current
 250 mA current limit capability
 Output clamping voltage 33 V
 30 mJ avalanche energy capability
 Enhanced cascading for multiple stages
 All registers cleared with single input
 Low power consumption
 ESD protection:
 HBM JDS-001 Class 2 exceeds 2500 V
 CDM JESD22-C101E exceeds 1000 V