PT7C4339 Datasheet, PDF (9/22 Pages) Pericom Semiconductor Corporation – Real-time Clock Module

PT7C4339/4339C
Real-time Clock Module
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4.2. Control and status register
Addr.
Description
D7
D6
D5
D4
(hex)
0E
Control
/EOSC
0
BBSQI
RS2
(default)
0
0
0
1
0F
Status
OSF
0
0
0
(default)
1
0
0
0
D3
D2
D1
D0
RS1
INTCN A2IE
1
0
0
A1IE
0
0
0
A2F
A1F
0
0
Undefined Undefined
1) Oscillator related bits
/EOSC
Enable oscillator bit.
/EOSC
Data
Read / Write
0 Starts the oscillator.
1 The oscillator is stopped.
Description
Default
2) BBSQI
Battery-Backed Square-Wave and Interrupt Enable bit.
BBSQI Data
Description
Read /
Write
0 The SQW/INT pin goes high impedance when VCC falls below the power-fail trip point.
Default
Enables the square wave or interrupt output when VCC is absent and the PT7C4339 is being powered by
1
the VBACKUP pin.
3) Square wave frequency selection bits
RS2, RS1
Square wave Rate Select. These bits control the frequency of the square-wave output when the square wave has been enabled.
RS2, RS1
Data
SQW output freq. (Hz)
00 1
Read / Write
01 4.096k
10 8.192k
11 32.768k
Default
4) OSF
Oscillator Stop Flag
Logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period of time and may be used to judge
the validity of the clock and calendar data. This bit is set to logic 1 anytime that the oscillator stops. The following are examples of
conditions that can cause the OSF bit to be set:
1) The first time power is applied.
2) The voltage present on VCC is insufficient to support oscillation.
3) The /EOSC bit is turned off.
4) External influences on the crystal (e.g., noise, leakage, etc.).
This bit remains at logic 1 until written to logic 0.
2015-08-0008
PT0508-1 08/24/15
9