PT7C4339 Datasheet, PDF (7/22 Pages) Pericom Semiconductor Corporation – Real-time Clock Module

PT7C4339/4339C
Real-time Clock Module
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Functional Description
1. Overview of Functions
1.1. Clock function
CPU can read or write data including the year (last two digits), month, date, day, hour, minute, and second. Any (two-digit)
year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2100.
For PT7C4339 on a power-on reset (POR), the time and date are set to 00:00:00 01/01/00 (hh:mm:ss DD/MM/YY) and the
Day register is set to 01.
1.2. Alarm function
This device has two alarm system (Alarm 1 and Alarm 2) that outputs interrupt signals from SQW/INT to CPU when the
date, day of the week, hour, minute or second correspond to the setting. Each of them may output interrupt signal separately at a
specified time. The alarm is be selectable between on and off for matching alarm or repeating alarm.
1.3. Programmable square wave output
A square wave output enable bit controls square wave output at pin 7. Frequencies are selectable: 1, 4.096k, 8.192k, 32.768
kHz.
1.4. Interface with CPU
Data is read and written via the I2C bus interface using two signal lines: SCL (clock) and SDA (data).
Since the output of the I/O pin SDA is open drain, a pull-up resistor should be used on the circuit board if the CPU output I/O
is also open drain.
The SCL's maximum clock frequency is 400 kHz, which supports the I2C bus's high-speed mode.
1.5. Oscillator fail detect
When oscillator fail, PT7C4339 OSF bit will be set.
1.6. Oscillator enable/disable
Oscillator can be enabled or disabled at the same time by /EOSC bit.
2. Operation
The PT7C4339 operates as a slave device on the serial bus. Access is obtained by implementing a START condition and
providing a device identification code followed by data. Subsequent registers can be accessed sequentially until a STOP condition
is executed. The device is fully accessible and data can be written and read when V_CC is greater than V_PF. However, when V_CC falls
below V_PF, the internal clock registers are blocked from any access. If V_PF is less than V_BACKUP, the device power is switched from
V_CC to V_BACKUP when V_CC drops below V_PF. If V_PF is greater than V_BACKUP, the device power is switched from V_CC to V_BACKUP
when V_CC drops below V_BACKUP. The registers are maintained from the V_BACKUP source until V_CC is returned to nominal levels.
3. Power Control
The power-control function is provided by a precise, temperature-compensated voltage reference and a comparator circuit
that monitors the V_CC level. The device is fully accessible and data can be written and read when V_CC is greater than V_PF. However,
when V_CC falls below V_PF, the internal clock registers are blocked from any access. If V_PF is less than V_BACKUP, the device power is
switched from V_CC to V_BACKUP when V_CC drops below V_PF. If V_PF is greater than V_BACKUP, the device power is switched from V_CC
to V_BACKUP when V_CC drops below V_BACKUP. The registers are maintained from the V_BACKUP source until V_CC is returned to nominal
levels (Table 2). After V_CC returns above V_PF, read and write access is allowed after t_REC (Figure 1). On the first application of
power to the device the time and date registers are reset to 01/01/00 01 00:00:00 (MM/DD/YY DOW HH:MM:SS).
Table 2:
Power Control Supply Condition
Read/Write Access
Power by
V_CC < V_PF, V_CC < V_BACKUP
V_CC < V_PF, V_CC > V_BACKUP
V_CC > V_PF, V_CC < V_BACKUP
V_CC > V_PF, V_CC > V_BACKUP
No
V_BACKUP
No
V_CC
Yes
V_CC
Yes
V_CC
2015-08-0008
PT0508-1 08/24/15
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