PT7C4339 Datasheet, PDF (17/22 Pages) Pericom Semiconductor Corporation – Real-time Clock Module

PT7C4339/4339C
Real-time Clock Module
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
The receiver (receiving side) captures data while the SCL line is at high level.
*Note: with caution that if the SDA data is changed while the SCL line is at high level, it will be treated as a START, RESTART,
or STOP condition.
b) Data acknowledge response (ACK signal)
When transferring data, the receiver generates a confirmation response (ACK signal, low active) each time an 8-bit data
segment is received. If there is no ACK signal from the receiver, it indicates that normal communication has not been established.
(This does not include instances where the master device intentionally does not generate an ACK signal.)
Immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the SCL line, the transmitter
releases the SDA line and the receiver sets the SDA line to low (= acknowledge) level.
SCL from Master
1
2
8
9
SDA from transmitter
(sending side)
Release SDA
SDA from receiver
(receiving side)
Low active
ACK signal
After transmitting the ACK signal, if the Master remains the receiver for transfer of the next byte, the SDA is released at the
falling edge of the clock corresponding to the 9th bit of data on the SCL line. Data transfer resumes when the Master becomes the
transmitter.
When the Master is the receiver, if the Master does not send an ACK signal in response to the last byte sent from the slave,
that indicates to the transmitter that data transfer has ended. At that point, the transmitter continues to release the SDA and awaits
a STOP condition from the Master.
5.4. Slave Address
The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select
pin, slave addresses are allocated to each device.
All communications begin with transmitting the [START condition] + [slave address (+ R/W specification)]. The receiving
device responds to this communication only when the specified slave address it has received matches its own slave address.
Slave addresses have a fixed length of 7 bits. See table for the details.
An R/W bit is added to each 7-bit slave address during 8-bit transfers.
Table
Slave address
Operation Transfer data
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1
R / W bit
bit 0
Read
Write
D1 h
1
1
0
1
0
0
0
D0 h
1 (= Read)
0 (= Write)
2015-08-0008
PT0508-1 08/24/15
17