PI3VDP411LST Datasheet, PDF (9/11 Pages) Pericom Semiconductor Corporation – Digital Video Level Shifter for dual mode DP signals w/ inverting buffer for HPD signal

PI3VDP411LST
Digital Video Level Shifter for dual mode DP
signals w/ inverting buffer for HPD signal
TMDS Outputs
The level shifter's TMDS outputs are required to meet HMDI 1.3 specifications.
The HDMI 1.3 Specification is assumed to be the correct reference in instances where this document conflicts
with the HDMI 1.3 specification.
Table 6: Differential Output Characteristics for TMDS_OUT signals
Symbol
V_H
V_L
V_SWING
I_OFF
T_R
T_F
T_SKEW-INTRA
T_SKEW-INTER
T_JIT
Parameter
Min
Single-ended AVCC-10mV
high level output
voltage
Single-ended AVCC-600mV
low level output
voltage
Single-ended 450mV
output swing
voltage
Single-ended
current in high-Z
state
Rise time
125ps
Fall time
125ps
Intra-pair
differential skew
Inter-pair lane-
to-lane output
skew
Jitter added to
TMDS signals
Nom
AVCC
AVCC-500mV
500mV
Max
AVCC+10mV
AVCC-400mV
600mV
10
0.4Tbit
0.4Tbit
30
100
25
Units Comments
V AVCC is the DC termina-
tion voltage in the HDMI
or DVI Sink. AVCC is
nominally 3.3V
V The open-drain output
pulls down from AVcc.
V Swing down from TMDS
termination voltage (3.3V
± 10%)
μA Measured with
TMDS outputs pulled
up to AVCC Max
(3.6V)through 50Ω resis-
tors.
ps Max Rise/Fall time
@2.7Gbps = 148ps.
125ps = 148-15%
ps Max Rise/Fall time
@2.7Gbps = 148ps.
125ps = 148-15%
ps This differential skew
budget is in addition to
the skew presented be-
tween D+ and D- paired
input pins. HDMI revision
1.3 source allowable in-
tra-pair skew is 0.15Tbit.
ps This lane-to-lane skew
budget is in addition to
skew between differential
input pairs
ps Jitter budget for TMDS
signals as they pass
through the level
shifter. 25ps = 0.056
Tbit at 2.25 Gb/s
07-0191
9
PS8906A
08/28/07