PI3VDP411LST Datasheet, PDF (8/11 Pages) Pericom Semiconductor Corporation – Digital Video Level Shifter for dual mode DP signals w/ inverting buffer for HPD signal

PI3VDP411LST
Digital Video Level Shifter for dual mode DP
signals w/ inverting buffer for HPD signal
Table 5: Differential Input Characteristics for IN_D and RX_IN signals
Symbol Parameter
Min Nom Max Units Comments
Tbit
Unit Interval
360
ps Tbit is determined by the display mode. Nom-
inal bit rate ranges from 250Mbps to 2.5Gbps
per lane. Nominal Tbit at 2.5 Gbps=400ps.
360ps=400ps-10%
V_RX-DIFFp-p Differential Input Peak 0.175
to Peak Voltage
1.200 V
VRX-DIFFp-p=2'|VRX-D+ x VRX-D-|
Applies to IN_D and RX_IN signals
T_RX-EYE
Minimum Eye Width at 0.8
IN_D input pair
Tbit The level shifter may add a maximum of
0.02UI jitter
V_CM-AC-pp AC Peak
Common Mode Input
Voltage
100 mV VCM-AC-pp = |VRX-D+ + VRX-D-|/2
- VRX-CM-DC.
VRX-CM-DC = DC(avg) of|VRX-D+ +
VRX-D-|/2
VCM-AC-pp includes all frequencies
above 30 kHz.
Z_RX-DC
40 50 60 Ω Required IN_D+ as well as IN_D- DC
impedance (50Ω ± 20% tolerance).
V_RX-Bias
0
2.0 V Intended to limit power-up stress on
chipset's PCIE output buffers.
Z_RX-HIGH-Z
100
kΩ Differential inputs must be in a high im-
pedance state when OE# is HIGH.
07-0191
8
PS8906A
08/28/07