PI2EQXDP101-A Datasheet, PDF (9/11 Pages) Pericom Semiconductor Corporation – 1 to 1 DisplayPort ReDriver

PI2EQXDP101-A
1 to 1 DisplayPort™ ReDriver™
Symbol
Parameters
Comments
Min. Typ. Max. Units
L_TX-SKEWIN-
TER_PAIR
Lane-to-Lane Output Skew at Tx package
pins
2
UI
L_TX-SKEWIN-
TRA_PAIR
Lane Intra-pair Output Skew at Tx pack-
age pins
20 ps
T_{TX-RISE_FALL}
_MISMATCH
_CHIPDIFF
Lane Intra-pair Rise-fall Time Mismatch
at Tx package pins.
C_TX
AC Coupling Capacitor
Informative. D+ rise to D- fall
mismatch and D+ fall to D- rise
mismatch.
All DisplayPort Main Link lanes
as well as AUX CH must be AC
coupled. AC coupling
capacitors must be placed on the 75
transmitter side. Placement
of AC coupling capacitors the
receiver side is optional.
5
%
200 nF
J_TOTAL
Total Output Jitter
0.32 UIp-p
Notes:
1. Refer to Pre-emphasis waveform. For embedded connection, support of programmable voltage swing levels is optional.
2. Refer to Pre-emphasis waveform for definition of differential voltage. Support of no preemphasis, 3.5 dB and 6.0 dB pre-emphasis is required.
Support of 9.5 dB level is optional. For embedded connection, support of programmable preemphasis levels is optional.
10-0194
9
P-0.3
07/09/10