PI2EQXDP101-A Datasheet, PDF (3/11 Pages) Pericom Semiconductor Corporation – 1 to 1 DisplayPort ReDriver

PI2EQXDP101-A
1 to 1 DisplayPort™ ReDriver™
AUX listener Register Assignment
AUXcommand are stored interpreted and stored in the registers, ReDriver will then be re-configured by de-
fault. Registers do not have a power-on default state.
Address Name
Description
Access
00100h
Link initialization field
AUX
LINK_BW_SET: Main Link Bandwidth Setting = Value x 0.27 Gbps per lane
Bits 7:0 = LINK_BW_SET
For DisplayPort version 1, revision 1a, only two values are supported. All
other values are reserved.
06h = 1.62 Gbps per lane
R/W
0Ah = 2.7 Gbps per lane
Source may choose either of the two link bandwidth as long as it does not ex-
ceed the capability of DisplayPort receiver as indicated in the receiver capabil-
ity field.
00101h Link initialization field
LANE_COUNT_SET
Bits3:0 = LANE_COUNT_SET
1h = One lane
2h = Two lanes
4h = Four lanes
R/W
For one-lane configuration, Lane0 is used. For 2-lane configuration, Lane0 and
Lane1 are used.
Bits7:4 = RESERVED. Read all 0’s.
TRAINING_LANE0_SET
Link Training Control_Lane0
Bits1:0 = DRIVE_CURRENT_SET
00 – Training Pattern 1 w/ level 0
01 – Training Pattern 1 w/ level 1
10 – Training Pattern 1 w/ level 2
11 – Training Pattern 1 w/ level 3
Bit2 = MAX_CURRENT_REACHED
Set to 1 when the maximum driven current setting is reached.
00103h DPCD Lane 0 status
Note: Support of programmable drive current is optional. For
example ifthere is only 1 level, then program Bits2:0 to 100 to
R/W
indicate to the receiver that Level 1 is the maximum drive current.
Support of independent drive current controlfor each lane is also
optional.
Bit4:3 = PRE-EMPHASIS_SET
00 = Training Pattern 2 w/o pre-emphasis
01 = Training Pattern 2 w/ pre-emphasis level 1
10 = Training Pattern 2 w/ pre-emphasis level 2
11 = Training Pattern 2 w/ pre-emphasis level 3
Bit5 = MAX_PRE-EMPHASIS_REACHED
00104h DPCD Lane 1 status
Lane setting for lane 1.
The definition is the same as lane 0
R/W
00105h DPCD Lane 2 status
Lane setting for lane 2.
The definition is the same as lane 0
R/W
00106h DPCD Lane 3 status
Lane setting for lane 3.
The definition is the same as lane 0
R/W
10-0194
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P-0.3
07/09/10