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PI2EQXDP101-A Datasheet, PDF (7/11 Pages) Pericom Semiconductor Corporation – 1 to 1 DisplayPort ReDriver
PI2EQXDP101-A
1 to 1 DisplayPort™ ReDriver™
Main Link Receiver (Main RX) Specifications
Symbol
Parameters
Comments
UI_High_Rate
UI_Low_Rate
Unit Interval for high bit
rate (2.7 Gbps / lane)
Unit Interval for low bit
rate (1.62 Gbps / lane)
Range is nominal +/-350ppm.
DisplayPort link RX does not
require local crystal for link clock
generation.
VRX-DIFFp-p-HR
Differential Peak-to-peak Input
Voltage at RX package pins
For High Bit Rate. Informative.
TRX-EYE-MEDI-
AN-to-
MAX-ITTER_CHIP
Maximum time between
the jitter median and
maximum deviation from
the median at Rx package
pins
TRX-EYE_CONN
TRX-EYE_CHIP
TRX-EYE-MEDI-
AN-to-
MAX-JITTER_CHIP
Minimum Receiver Eye Width
at RX-side connector pins
Minimum Receiver Eye Width
at RX package pins
Maximum time between the
jitter median and maximum
deviation from the median at RX
package
pins
Note 1
Note 1
Note 1
VRX-DC-CM
RX DC Common Mode Voltage
Common mode voltage is equal to
Vbias_Rx voltage
ZRX-DC
RLRX-DIFF
LRX-SKEW-
INTER_PAIR
DC Input Resistance
Differential Return Loss at
0.675GHz at RX package pins
Differential Return Loss at
1.35GHz at RX package pins
Lane-to-Lane Output Skew at
RX package pins
Straight loss line between 0.675
GHz and 1.35 GHz
Straight loss line between 0.675
GHz and 1.35 GHz
Maximum skew limit between
different RX lanes of a
DisplayPort link.
LRX-SKEW-
INTRA_PAIR High-
Bit-Rate
LRX-SKEW-
INTRA_PAIR_Re-
duced-Bit-Rate
Lane Intra-pair Output Skew at
RX package pins
Lane Intra-pair Output Skew at
RX package pins
For High Bit Rate Maximum skew
limit between D+ and D- of the
same lane.
For Reduced Bit Rate
Maximum skew limit between
D+ and D- of the same lane.
Min.
120
0.25
0.22
0
45
12
9
Typ.
370
617
50
Max.
Units
ps
ps
1500 mV
0.265 UI
UI
UI
0.39 UI
2.0
V
55
dB
dB
5200 ps
100 ps
300 ps
Note:
1. For Reduced Bit Rate (1- TRX-EYE_CONN) specifies the allowable TJ. TRX-EYE-MEDIAN-to-MAX-JITTER specifies the total allowable DJ
10-0194
7
P-0.3
07/09/10