PE3240 Datasheet, PDF (9/12 Pages) Peregrine Semiconductor Corp. – 2.2 GHz UltraCMOS™ Integer-N PLL for Low Phase Noise Applications

PE3240
Product Specification
Table 7. Primary Register Programming
Interface Mode _Enh
R5
R4
M8
M7 Pre_en M6 M5
M4
M3
M2
M1
M0
R3
R2
R1
R0
A3
A2
A1
A0
Serial*
1
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.
MSB (first in)
(last in) LSB
Table 8. Enhancement Register Programming
Interface
Mode
Enh
Reserved
Reserved
fp Output
Serial*
0
B0
B1
B2
Power
down
B3
Counter
load
B4
MSEL
output
B5
fc output
B6
*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.
Reserved
B7
MSB (first in)
(last in) LSB
Figure 7. Serial Interface Mode Timing Diagram
Sdata
E_WR
t_EC
t_CE
Sclk
S_WR
t_DSU
t_DHLD
t_ClkH
t_ClkL
t_CWR
t_PW
t_WRC
Document No. 70-0034-02 │ www.psemi.com
©2006 Peregrine Semiconductor Corp. All rights reserved.
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