PE3240 Datasheet, PDF (2/12 Pages) Peregrine Semiconductor Corp. – 2.2 GHz UltraCMOS™ Integer-N PLL for Low Phase Noise Applications

PE3240
Product Specification
Figure 2. Pin Configuration (Top View)
V_DD ¹
Enh ²
S_WR ³
Sdata ⁴
Sclk ⁵
GND ⁶
FSELS ⁷
E_WR ⁸
V_DD ⁹
F_in ¹⁰
20 _fr
19 _GND
18 _{PD_U}
17 _{PD_D}
16 _VDD
15 _Dout
14 _LD
13 _Cext
12 _GND
11 _Fin
Figure 3. Package Type
20-lead TSSOP
Table 1. Pin Descriptions
Pin No. Pin Name Type
Description
1
VDD
(Note 1) Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing required.
2
Enh
Input
Enhancement mode. When asserted low (“0”), enhancement register bits are functional. Internal 70 kΩ pull-
up resistor.
3
S_WR
Input
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary register data are
transferred to the secondary register on S_WR rising edge.
4
Sdata
Input
Binary serial data input. Input data entered MSB first.
5
Sclk
Input
Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “low”) or the 8-bit
enhancement register (E_WR “high”) on the rising edge of Sclk.
6
GND
Ground.
Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for programming of internal
7
FSELS
Input
counters. Internal 70 kΩ pull-down resistor.
8
E_WR
Input
Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into the
enhancement register on the rising edge of Sclk. Internal 70 kΩ pull-down resistor.
9
VDD
(Note 1) Same as pin 1.
10
Fin
Input
Prescaler input from the VCO. Max frequency input is 2.2 GHz.
11
F_in
Input
Prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be
connected in series with a 50 Ω resistor to the ground plane.
12
GND
Ground.
13
Cext
Output
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ series resistor. Connecting Cext to
an external capacitor will low pass filter the input to the inverting amplifier used for driving LD.
14
LD
Output
Lock detect is an open drain logical inversion of CEXT. When the loop is in lock, LD is high impedance,
otherwise LD is a logic low (“0”).
15
Dout
Output Data out function, Dout, enabled in enhancement mode.
16
VDD
(Note 1) Same as pin 1.
©2006 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 12
Document No. 70-0034-02 │ UltraCMOS™ RFIC Solutions