PE3240 Datasheet, PDF (7/12 Pages) Peregrine Semiconductor Corp. – 2.2 GHz UltraCMOS™ Integer-N PLL for Low Phase Noise Applications

PE3240
Product Specification
Functional Description
The PE3240 consists of a prescaler, counters, a
phase detector and control logic. The dual
modulus prescaler divides the VCO frequency by
either 10 or 11, depending on the value of the
modulus select. Counters “R” and “M” divide the
reference and prescaler output, respectively, by
integer values stored in a 20-bit register. An
additional counter (“A”) is used in the modulus
select logic.
Figure 6. Functional Block Diagram
The phase-frequency detector generates up and
down frequency control signals. Data is written
into the internal registers via the three wire serial
bus. There are also various operational and test
modes and a lock detect output.
f_r
R Counter
(6-bit)
f_c
Sdata
Control
Pins
Control
Logic
R(5:0)
M(8:0)
A(3:0)
Phase
Detector
Modulus
Select
F_in
F_in
10/11
Prescaler
M Counter
(9-bit)
f_p
PD_U
PD_D
2 kΩ
LD
Cext
Document No. 70-0034-02 │ www.psemi.com
©2006 Peregrine Semiconductor Corp. All rights reserved.
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