PE3240 Datasheet, PDF (3/12 Pages) Peregrine Semiconductor Corp. – 2.2 GHz UltraCMOS™ Integer-N PLL for Low Phase Noise Applications

PE3240
Product Specification
Table 1. Pin Descriptions (continued)
Pin No.
17
18
Pin Name
PD_D
PD_U
Type
Output
Output
PD_D pulses down when fp leads fc.
PD_U pulses down when fc leads fp.
Description
19
GND
Ground.
20
fr
Input
Reference frequency input.
Note 1: VDD pins 1, 9, and 16 are connected by diodes and must be supplied with the same positive voltage level.
Table 2. Absolute Maximum Ratings
Symbol Parameter/Conditions Min Max Units
VDD
Supply voltage
VI
Voltage on any input
II
DC into any input
-0.3 4.0
V
-0.3
VDD +
0.3
V
-10 +10 mA
IO
DC into any output
-10 +10 mA
Tstg
Storage temperature range -65 150 °C
Table 3. Operating Ratings
Symbol Parameter/Conditions Min Max Units
VDD
Supply voltage
2.85 3.15
V
TA
Operating ambient
temperature range
-40 85
°C
Table 4. ESD Ratings
Symbol
Parameter/Conditions
Level Units
VESD
ESD voltage human body model
(Note 1)
1000
V
Note 1: Periodically sampled, not 100% tested. Tested per
MIL-STD-883, M3015 C2
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Document No. 70-0034-02 │ www.psemi.com
©2006 Peregrine Semiconductor Corp. All rights reserved.
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