PE83336 Datasheet, PDF (8/14 Pages) Peregrine Semiconductor Corp. – 3.0 GHz Integer-N PLL for Low Phase Noise Applications

Table 7. Phase Noise Test
Test name
Phase Noise
Conditions
100 Hz Offset
1000 Hz Offset
Max
-80
-87
Units
dBc/Hz
dBc/Hz
Functional Description
The PE83336 consists of a prescaler, counters, a
phase detector and control logic. The dual modulus
prescaler divides the VCO frequency by either 10 or
11, depending on the value of the modulus select.
Counters “R” and “M” divide the reference and
prescaler output, respectively, by integer values
stored in a 20-bit register. An additional counter
Figure 3. Functional Block Diagram
f_r
R Counter
(6-bit)
PE83336
Product Specification
(“A”) is used in the modulus select logic. The phase-
frequency detector generates up and down
frequency control signals. The control logic includes
a selectable chip interface. Data can be written via
serial bus, parallel bus, or hardwired direct to the
pins. There are also various operational and test
modes and lock detect.
f_c
D(7:0)
Sdata
Control
Pins
Control
Logic
R(5:0)
M(8:0)
A(3:0)
Phase
Detector
Modulus
Select
F_in
10/11
M Counter
F_in
Prescaler
(9-bit)
PD_U
PD_D
LD
Cext
2kΩ
f_p
Copyright  Peregrine Semiconductor Corp. 2003
Page 8 of 14
File No. 70/0137~01A
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