PE83336 Datasheet, PDF (2/14 Pages) Peregrine Semiconductor Corp. – 3.0 GHz Integer-N PLL for Low Phase Noise Applications

Figure 2. Pin Configuration
D₀, M₀
D₁, M₁
D₂, M₂
D₃, M₃
V_DD
V_DD
S_WR, D₄, M₄
Sdata, D₅, M₅
Sclk, D₆, M₆
FSELS, D₇, Pre_en
GND
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
18 19 20 21 22 23 24 25 26 27 28
f_c
V_DD_f_c
PD_U
PD_D
V_DD
C_ext
V_DD
D_out
V_DD_f_p
f_p
GND
PE83336
Product Specification
44-lead CQFJ
Table 1. Pin Descriptions
Pin No.
(44-lead
CQFJ)
1
2
3
4
5
6
7
8
9
10
11
12
13
Pin
Name
V_DD
R₀
R₁
R₂
R₃
GND
D₀
M₀
D₁
M₁
D₂
M₂
D₃
M₃
V_DD
V_DD
S_WR
Interface
Mode
ALL
Direct
Direct
Direct
Direct
ALL
Parallel
Direct
Parallel
Direct
Parallel
Direct
Parallel
Direct
ALL
ALL
Serial
Type
(Note 1)
Input
Input
Input
Input
(Note 1)
Input
Input
Input
Input
Input
Input
Input
Input
(Note 1)
(Note 1)
Input
Copyright  Peregrine Semiconductor Corp. 2003
Page 2 of 14
Description
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing recommended.
R Counter bit0 (LSB).
R Counter bit1.
R Counter bit2.
R Counter bit3.
Ground.
Parallel data bus bit0 (LSB).
M Counter bit0 (LSB).
Parallel data bus bit1.
M Counter bit1.
Parallel data bus bit2.
M Counter bit2.
Parallel data bus bit3.
M Counter bit3.
Same as pin 1.
Same as pin 1.
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary
File No. 70/0137~01A
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UTSi CMOS RFIC SOLUTIONS