PE83336 Datasheet, PDF(10/14 Page) Peregrine Semiconductor Corp. – 3.0 GHz Integer-N PLL for Low Phase Noise Applications

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PE83336 Datasheet, PDF (10/14 Pages) Peregrine Semiconductor Corp. – 3.0 GHz Integer-N PLL for Low Phase Noise Applications

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PE83336

Product Specification

inadvertent control changes during serial loading,

with buffer capture of the serially entered data

performed on the falling edge of E_WR according to

the timing diagram shown in Figure 5. After the

falling edge of E_WR, the data provide control bits

as shown in Table 8 with bit functionality enabled by

asserting the Enh input âlowâ.

Direct Interface Mode

Direct Interface Mode is selected by setting the

Bmode input âhighâ.

Counter control bits are set directly at the pins as

shown in Table 7. In Direct Interface Mode, main

counter inputs M7 and M8, and R Counter inputs R4

and R5 are internally forced low (â0â).

Table 8. Primary Register Programming

Interface

Mode

Enh

Bmode Smode R5

M7 Pre_en M6

Parallel 1

M2_WR rising edge load

M1_WR rising edge load

A_WR rising edge load

D3 D2 D1 D0

D0 D7 D6 D5 D4 D3 D2 D1 D0

Serial*

B10 B11 B12 B13 B14 B15 B16 B17 B18 B19

Direct

0 Pre_en M6 M5 M4 M3 M2 M1 M0 R3 R2 R1 R0 A3 A2 A1 A0

*Serial data clocked serially on Sclk rising edge while E_WR âlowâ and captured in secondary register on S_WR rising edge.

MSB (first in)

Table 9. Enhancement Register Programming

Interface

Mode

Enh

Bmode Smode

Reserved

Power

down

Counter

load

MSEL

output

Prescaler

output

Parallel 0

E_WR rising edge load

Serial*

*Serial data clocked serially on Sclk rising edge while E_WR âhighâ and captured in the double buffer on E_WR falling edge.

(last in) LSB

fc, fp OE

MSB (first in)

(last in) LSB

Page 10 of 14

File No. 70/0137~01A

UTSi CMOS RFIC SOLUTIONS

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