PE83336 Datasheet, PDF (3/14 Pages) Peregrine Semiconductor Corp. – 3.0 GHz Integer-N PLL for Low Phase Noise Applications

PE83336
Product Specification
Pin No.
(44-lead
CQFJ)
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Pin
Name
Interface
Mode
Type
D₄
M₄
Sdata
D₅
M₅
Sclk
D₆
M₆
FSELS
D₇
Pre_en
GND
FSELP
A₀
E_WR
A₁
M2_WR
A₂
Smode
A₃
Bmode
V_DD
M1_WR
Parallel
Direct
Serial
Parallel
Direct
Serial
Parallel
Direct
Serial
Parallel
Direct
ALL
Parallel
Direct
Serial
Parallel
Direct
Parallel
Direct
Serial,
Parallel
Direct
ALL
ALL
Parallel
A_WR
Parallel
Hop_WR
F_in
Serial,
Parallel
ALL
F_in
ALL
GND
ALL
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
(Note 1)
Input
Input
Input
Input
Input
Description
register data are transferred to the secondary register on S_WR or Hop_WR rising edge.
Parallel data bus bit4
M Counter bit4
Binary serial data input. Input data entered MSB first.
Parallel data bus bit5.
M Counter bit5.
Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “low”) or
the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk.
Parallel data bus bit6.
M Counter bit6.
Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for
programming of internal counters while in Serial Interface Mode.
Parallel data bus bit7 (MSB).
Prescaler enable, active “low”. When “high”, F_in bypasses the prescaler.
Ground.
Selects contents of primary register (FSELP=1) or secondary register (FSELP=0) for
programming of internal counters while in Parallel Interface Mode.
A Counter bit0 (LSB).
Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked
into the enhancement register on the rising edge of Sclk.
Enhancement register write. D[7:0] are latched into the enhancement register on the rising
edge of E_WR.
A Counter bit1.
M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising edge of
M2_WR.
A Counter bit2.
Selects serial bus interface mode (Bmode=0, Smode=1) or Parallel Interface Mode
(Bmode=0, Smode=0).
A Counter bit3 (MSB).
Selects direct interface mode (Bmode=1).
Same as pin 1.
M1 write. D[7:0] are latched into the primary register (Pre_en, M[6:0]) on the rising edge of
M1_WR.
A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising edge of
A_WR.
Hop write. The contents of the primary register are latched into the secondary register on
the rising edge of Hop_WR.
Prescaler input from the VCO. 3.0 GHz max frequency.
Prescaler complementary input. A bypass capacitor should be placed as close as possible
to this pin and be connected in series with a 50 Ω resistor directly to the ground plane.
Ground.
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Copyright  Peregrine Semiconductor Corp. 2003
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