MN101E56 Datasheet, PDF (8/13 Pages) Panasonic Semiconductor – 8-bit Single-chip Microcontroller

MN101E56/57/76 シリーズ
 Features (continued)
 Serial interface (continued)
Serial interface 4 (Multi master IIC / Synchronous serial interface)
Synchronous serial interface
Transfer clock source:
fpll-div/2, fpll-div/4, fpll-div/8, fpll-div/32, fs/2, fs/4, Timer 0 to 4, Timer A output divided by 1, 2, 4, 8, 16, External clock
MSB/LSB first selectable, 1 to 8 bits of arbitrary transfer
Continuous transmission, continuous reception, continuous transmission and reception are available.
Multi master IIC
7, 10-bit slave address is settable
General call communication mode is supported
 Auto reset circuit
 Low voltage detection circuit
 Clock Monitoring Function
 LED driver: 8 sets
 LCD driver
Segment output
MN101EF76K: Max. 55 pins (SEG0 to SEG54)
MN101EF57G: Max. 41 pins (SEG0 to SEG40)
MN101EF56K: Max. 55 pins (SEG0 to SEG54)
Segment output pins can be switched to I/O ports in 1 bit.
* At reset, Segment outputs are input ports.
Common output: 4 pins
COM0 to 3 can be switched to I/O ports in 1 bit.
Display mode selection
Static
1/2 duty, 1/2 bias
1/3 duty, 1/3 bias
1/4 duty, 1/3 bias
LCD driver clock
When the source clock is the main clock (fpll)
1/2¹⁸, 1/2¹⁷, 1/2¹⁶, 1/2¹⁵, 1/2¹⁴, 1/2¹³, 1/2¹², 1/2¹¹
When the source clock is the sub clock (fslow)
1/2⁹, 1/2⁸, 1/2⁷, 1/2⁶
Timer 0 to 4, Timer A output
LCD power supply
LCD power supply is separated from V_DD5 . (can be used when V_LC1 ≤ V_DD5)
External power supply voltage can be selectable. (Supply voltage is supplied from V_LC1, V_LC2, and V_LC3)
Internal dividing resistors (External power supply voltage is divided the voltage input to V_LC1 by internal resistors.)
Ver. BEM
8