MN101E56 Datasheet, PDF (7/13 Pages) Panasonic Semiconductor – 8-bit Single-chip Microcontroller

MN101E56/57/76 シリーズ
 Features (continued)
 Serial interface
MN101EF76K: 5 systems
MN101EF57G: 4 systems
MN101EF56K: 5 systems
Serial interface 0 (Hardware LIN / Full duplex UART / Synchronous serial interface)
Synchronous serial interface
Transfer clock source:
fpll-div/2, fpll-div/4, fpll-div/16, fpll-div/64, fs/2, fs/4, Timer 0 to 4, Timer A output divided by 1, 2, 4, 8, 16, External clock
MSB/LSB first selectable, 1 to 8 bits of arbitrary transfer
Continuous transmission, continuous reception, continuous transmission and reception are available.
Full duplex UART (Baud rate timer: selected from timer 0 to 4, or timer A)
Parity check, overrun error/framing error are detected
Transfer bits 7 to 8 are selectable
Hardware LIN
Synch Break generation, Wake-up detection, Synch Break detection, Synch Field measurement are available
Serial interface 1 (Full duplex UART / Synchronous serial interface)
Synchronous serial interface
Transfer clock source:
fpll-div/2, fpll-div/4, fpll-div/16, fpll-div/64, fs/2, fs/4,Timer 0 to 4, Timer A output divided by 1, 2, 4, 8, 16, External clock
MSB/LSB first selectable, 1 to 8 bits of arbitrary transfer
Continuous transmission, continuous reception, continuous transmission and reception are available.
Full duplex UART (Baud rate timer: selected from timer 0 to 4, or timer A)
Parity check, overrun error/framing error are detected
Transfer bits 7 to 8 are selectable
Serial interface 2 (Full duplex UART / Synchronous serial interface)
Synchronous serial interface
Transfer clock source:
fpll-div/2, fpll-div/4, fpll-div/16, fpll-div/64, fs/2, fs/4, Timer 0 to 4, Timer A output divided by 1, 2, 4, 8, 16, External clock
MSB/LSB first selectable, 1 to 8 bits of arbitrary transfer
Continuous transmission, continuous reception, continuous transmission and reception are available.
Full duplex UART (Baud rate timer: selected from timer 0 to 4, or timer A)
Parity check, overrun error/framing error are detected
Transfer bits 7 to 8 are selectable
Serial interface 3 (Full duplex UART / Synchronous serial interface) * Function in MN101EF76K and MN101EF56K
Synchronous serial interface
Transfer clock source:
fpll-div/2, fpll-div/4, fpll-div/16, fpll-div/64, fs/2, fs/4, Timer 0 to 4, Timer A output divided by 1, 2, 4, 8, 16, External clock
MSB/LSB first selectable, 1 to 8 bits of arbitrary transfer
Continuous transmission, continuous reception, continuous transmission and reception are available.
Full duplex UART (Baud rate timer: selected from timer 0 to 4, or timer A)
Parity check, overrun error/framing error are detected
Transfer bits 7 to 8 are selectable
Ver. BEM
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