MN101E56 Datasheet, PDF (2/13 Pages) Panasonic Semiconductor – 8-bit Single-chip Microcontroller

MN101E56/57/76 シリーズ
 Features
 ROM / RAM capacity
MN101EF76K: ROM 256 KB / RAM 10 KB
MN101EF57G: ROM 128 KB / RAM 6 KB
MN101EF56K: ROM 256 KB / RAM 10 KB
 Package:
MN101EF76K: LQFP128-P-1818C (18 mm × 18 mm / 0.5 mm pitch)
MN101EF57G: LQFP080-P-1414A (14 mm × 14 mm / 0.65 mm pitch)
TQFP080-P-1212F (12 mm × 12 mm / 0.5 mm pitch)
MN101EF56K: QFP100-P-1818B (18 mm × 18 mm / 0.65 mm pitch)
 Machine Cycle:
High-speed mode
0.05 ms / 20 MHz (2.7 V to 5.5 V)
0.125 ms / 8 MHz (1.8 V to 5.5 V)
Low-speed mode
62.5 ms / 32 kHz (1.8 V to 5.5 V)
 Clock Gear Circuit:
Internal system clock speed is changeable by selecting division ratio of oscillation clock. (Divided by 1, 2, 4, 16, 32, 64, 128)
 Oscillation Circuit: 4 types
High-speed (Internal oscillation: frc), High-speed (crystal/ceramic: fosc),
Low-speed (Internal oscillation: frcs), Low-speed (crystal/ceramic: fx)
High-speed internal oscillation 20 MHz / 16 MHz (selectable)
Low-speed internal oscillation 30 kHz
 Clock Multiplication Circuit:
PLL circuit output clock (fpll) fosc multiplied by 2, 3, 4, 5, 6, 8, 10,1/2 × frc multiplied by 4, 5 enabled
* When clock multiplication circuit is not used, fpll = fosc or fpll = frc
* Selectable from high-speed clock for peripheral functions (fpll-div) fpll, fpll divided by 2, 4, 8, 16
 Memory bank
Data memory space is expanded by the bank system.
Bank for the source address / Bank for the destination address.
 Operation Mode
NORMAL mode (high-speed mode)
PLL mode
SLOW mode (low-speed mode)
HALT mode
STOP mode
and operation clock switching
 Operating Voltage
1.8 V to 5.5 V
 Operating Ambient Temperature:
-40°C to +85°C
Ver. BEM
2