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FG654301 Datasheet, PDF (2/7 Pages) Panasonic Semiconductor – Silicon N-channel MOS FET
FG654301
This product complies with the RoHS Directive (EU 2002/95/EC).
 Electrical Characteristics Ta = 25°C±3°C
 FET1
Parameter
Symbol
Conditions
Min Typ Max Unit
Drain-source surrender voltage
Drain-source cutoff current
Gate-source cutoff current
Gate threshold voltage
VDSS
IDSS
IGSS
VTH
ID = 1 mA, VGS = 0
VDS = 30 V, VGS = 0
VGS = ±10 V, VDS = 0
ID = 1.0 mA, VDS = 3.0 V
30
V
1.0
mA
±10
mA
0.5
1.0
1.5
V
Drain-source ON resistance
Forward transfer admittance
Short-circuit input capacitance (Common source)
RDS(on)
Yfs
Ciss
ID = 10 mA, VGS = 2.5 V
ID = 10 mA, VGS = 4.0 V
ID = 10 mA, VDS = 3.0 V
3
6
W
2
3
20
55
mS
12
pF
Short-circuit output capacitance (Common source) Coss VDS = 3 V, VGS = 0, f = 1 MHz
7
pF
Reverse transfer capacitance (Common source) Crss
3
pF
Turn-on time *
ton VDD = 3 V, VGS = 0 V to 3 V, ID = 10 mA
100
ns
Turn-off time *
toff VDD = 3 V, VGS = 3 V to 0 V, ID = 10 mA
100
ns
Note) 1. Measuring methods are based on JAPANESE INDUSTRIAL STANDARD JIS C 7030 measuring methods for transistors.
2. *: Test circuit
VDD = 3 V
VGS = 0 V to 3 V
VIN
G
50 Ω
ID = 10 mA
RL = 300 Ω
VIN
D
VOUT
VOUT
90%
10%
10%
90%
S
ton
toff
 FET2
Parameter
Symbol
Conditions
Min Typ Max Unit
Drain-source surrender voltage
Drain-source cutoff current
Gate-source cutoff current
VDSS
IDSS
IGSS
ID = -1 mA, VGS = 0
VDS = -30 V, VGS = 0
VGS = ±10 V, VDS = 0
-30
V
-1.0
mA
±10
mA
Gate threshold voltage
Drain-source ON resistance
VTH
RDS(on)
ID = -1.0 mA, VDS = -3.0 V
ID = -10 mA, VGS = -2.5 V
ID = -10 mA, VGS = -4.0 V
- 0.5 -1.0 -1.5
V
7
17
W
4
7
Forward transfer admittance
Yfs ID = -10 mA, VDS = -3.0 V
20
40
mS
Short-circuit input capacitance (Common source) Ciss
12
pF
Short-circuit output capacitance (Common source) Coss VDS = -3 V, VGS = 0, f = 1 MHz
7
pF
Reverse transfer capacitance (Common source) Crss
3
pF
Turn-on time *
ton VDD = -3V,VGS = 0Vto -3V, ID = -10 mA
100
ns
Turn-off time *
toff VDD = -3V,VGS = -3Vto 0V, ID = -10 mA
100
ns
Note) 1. Measuring methods are based on JAPANESE INDUSTRIAL STANDARD JIS C 7030 measuring methods for transistors.
2. *: Test circuit
VGS = 0 V to −3 V
VIN
G
50 Ω
VDD = −3 V
ID = −10 mA
RL = 300 Ω
D
VOUT
10%
VIN
VOUT 10%
90%
90%
S
td(on) tr
td(off) tf
2
Ver. AED