MN103SFM9K Datasheet, PDF (11/25 Pages) Panasonic Semiconductor – 32-bit Single-chip Microcontroller

1.3.3 Pin Functions
Table:1.3.2 Pin Functions
Name
VDD
VDD
VDD
VDD
VDD
TQFP 48
Pin No.
I/O
17
-
40
41
65
94
Other Function
VDD2
42
VDD2
98
VSS
15
VSS
38
VSS
67
VSS
96
VPPEX
39
OSC1
37
OSC0
36
NRST
48
-
-
-
input -
output
input -
P10
43
I/O
IRQ04/ EXTRG0
P11
44
IRQ05/ EXTRG1
P12
45
IRQ06
P13
46
IRQ07
P14
47
IRQ08
P15
49
TM6IO
P16
50
TM7IO
P17
51
SBO2
P20
52
I/O
SBT2
P21
53
SBI2
P22
54
SBO1
P23
55
SBT1
P24
56
SBI1
P25
57
SBO0
P26
58
SBT0
P27
59
SBI0
P30
60
I/O
TM0IO
P31
61
TM1IO
P32
62
TM2IO
P33
63
TM3IO
P34
64
TM4IO
P35
66
TM5IO
P36
68
TM8AIO
P37
69
TM8BIO
MN103SFM9K
32-bit Single-chip Microcontroller
PubNo. 232M9-010E
Function
Description
Power supply pin
Power supply pin
Power supply pin
Power pin for 5 V, digital IO.
Apply 5 V to all of pins and connect capacitor
of over 10 μF between all of the VDD and
VSS pins. (allocate near the pins)
It is recommended that total capacitance
between all of the VDD and VSS is more than
10-times capacitance between all of the
VDD2 and VSS.
Power pin for 1.8 V, digital IO
Connect capacitor of over 1 μF between all of
the VDD2 and VSS pins.
(allocate near the pins)
GND for digital
Power supply pin
Clock input pin
Clock output pin
Reset pins
(negative logic)
I/O port 1
Power for flash EEPROM
Connect with VDD.
Extend ceramic or crystal oscillators or input
a clock to OSC1.
This pin resets the chip when power is turned
on and contains an internal pull-up resistor.
Setting this pin “L” level initialize the internal
state of the device. Thereafter, setting the
input to “H” level releases the reset. The
hardware waits for the system clock to
stabilize, then processes the reset interrupt.
Connect capacitor of over 0.1 μF between
NRST and VSS pins.
8-bit CMOS I/O port.
Each bit can be set individually as either an
input or output by the P1DIR register.
A pull-up resistor for each bit can be selected
individually by the P1PLU register.
At reset, the input mode (P10 to P17) is
selected, and pull-up resistor is disable.
I/O port 2
8-bit CMOS I/O port.
Each bit can be set individually as either an
input or output by the P2DIR register.
A pull-up resistor for each bit can be selected
individually by the P2PLU register.
At reset, the input mode (P20 to P27) is
selected, and pull-up resistor is disable.
I/O port 3
8-bit CMOS I/O port.
Each bit can be set individually as either an
input or output by the P3DIR register.
A pull-up resistor for ech bit can be selected
individually by the P3PLU register.
At reset, the input mode (P30 to P37) is
selected, pull-up resistor is disable.
Publication date: August 2014