OXCF950 Datasheet, PDF (9/66 Pages) Oxford Semiconductor – Single full-duplex asynchronous channel 128-byte deep transmitter / receiver FIFO

OXFORD SEMICONDUCTOR LTD.
OXCF950 rev B DATA SHEET V 1.0
28 (E5)
30 (D5)
21 (F4)
20 (H4)
34 (C6)
35 (C4)
36 (B6)
33 (E4)
EEPROM
13 (H1)
14 (G2)
16 (G3)
15 (H2)
Miscellaneous Pins
18, 31
(G4, D6)
17 (H3)
Power and Ground²
39, 19, 8
(A5, E3, D3)
I
DSR#
Rx_Clk_In
I
RI#
Tx_Clk_In
O
XTLO
I
XTLI
O
LBCS#
O
OUT1#
I
A[5]
O
LBRD# ²
O
RXRDY#
I
A[6]
O
LBWR#
O
TXRDY#
I
A[7]
O
LBRST²
O
OUT2#
I
A[4]
O
EE_CK
O
EE_CS
I
EE_DI
O
EE_DO
I/O MIO[1:0]
I
MODE
G
GND
the transmitter will complete th e current character and enter
the idle mode until the CTS# pin is reasserted. Note: flow
control characters are transmitted regardless of the state of
the CTS# pin.
Active-low modem data-set-ready input. If automated DSR#
flow control is enabled, upon de-assertion of the DSR# pin,
the transmitter will complete the current character and enter
the idle mode until the DSR# pin is reasserted. Note: flow
control characters are transmitted regardless of the state of
the DSR# pin
External receiver clock for isochronous applications. The
Rx_Clk_In is selected when register CKS[1:0] = ’01’
Active-low modem Ring-indicator input
External transmitter clock. This clock can be used by the
transmitter (and indirectly by the receiver) when register
CKS[6] = ‘1’.
Crystal oscillator output
Crystal oscillator input or external clock pin. Frequency
1.8MHz -> 60MHz.
For 1.8 to 20 MHz, a crystal may be used. Above this range,
an external clock source is required.
Local Bus Mode : Active low local bus Chip select
C950 Mode: Active low OUT1
Normal Mode : Address bit 5
Local Bus Mode : Active-low local bus read enable
C950 Mode:Active low RXRDY
Normal Mode : Address bit 6
Local Bus Mode : Active-low local bus write enable
C950 Mode:Active low TXRDY
Normal Mode : Address bit 7
Local Bus Mode : Active high local bus Reset
C950 Mode:Active low OUT2
Normal Mode : Address bit 4
EEPROM clock. In normal operation the frequency of this is
XTLI input clock / 64. The clock is only active during
configuration following reset.
EEPROM active-high Chip Select.
EEPROM data in. This pin should be pulled up using 1-10k
resistor if an EEPROM is used, or pulled up/down depending
upon required stand-alone mode..
EEPROM data out.
User defined IO pins.
Note: that if enabled, MIO[1:0] can be used as an interrupt
inputs.
Local Bus mode select. Note Local Bus mode requires
indirect addressing, which is only supported by the PCMCIA
specification
‘0’ = Normal Mode (CF/PCMCIA compatible)
‘1’ = Local Bus Mode (PCMCIA compatible)
Ground (0 Volts). The GND pins should be tied to ground
Page 9