OXCF950 Datasheet, PDF (16/66 Pages) Oxford Semiconductor – Single full-duplex asynchronous channel 128-byte deep transmitter / receiver FIFO

OXFORD SEMICONDUCTOR LTD.
OXCF950 rev B DATA SHEET V 1.0
Each of the local configuration registers are explained in the following sections. The offsets assume normal or local bus mode,
and these are the offsets that should be used when accessing the registers via the EEPROM.
EEPROM Status and Control register ‘ESC’(Offset 0x08)
This register defines the control on the serial EEPROM. The individual bits are described in Table 7.
Bits
Description
Read/Write
Reset
EEPROM PCMCIA
7:6
Reserved
-
R
000
5
EEPROM Overrun.
-
R
0
Set when an invalid EEPROM image causes the end of the EEPROM to be
read before the end of the programming sequence. In this state the
OXCF950 is set as though no EEPROM is attached.
This feature is new to OXCF950 rev B
4
EEPROM Data In.
-
R
X
For reads from the EEPROM this input bit is the output-data (DO) of the
external EEPROM connected to EE_DI pin
3
EEPROM Data Out.
-
R/W
0
For writes to the EEPROM, this output bit feeds the inpu-tdata of the
external EEPROM (DI). This bit is output on the devices EE_DO and
clocked into the EEPROM by EE_CK
2
EEPROM Clock.
-
R/W
0
For reads or writes to the external EEPROM toggle this bit to generate an
EEPROM clock (EE_CK pin)
1
EEPROM Chip Select.
-
R/W
0
When ‘1’ the EEPROM chip select pin EE_CS is activated (high). When ‘0’
EE_CS is de-activated (low)
0
EEPROM Valid
A ‘1’ indicates that a valid EEPROM program header is present
-
R
X
Table 7: EEPROM Status and Control Register
Multi-Purpose I/O Configuration register ‘MIC’ (Offset 0x09)
This register configures the operation for the multi-purpose I/O pins ‘MIO[1:0]’ as follows
Bits
Description
7:4
Reserved
3:2
MIO1 Configuration register
00 -> MIO1 is a non-inverting input pin
01 -> MIO1 is an inverting input pin
10 -> MIO1 is an output pin driving ‘0’
11 -> MIO1 is an output pin driving ‘1’
1:0
MIO0 Configuration register
00 -> MIO0 is a non-inverting input pin
01 -> MIO0 is an inverting input pin
10 -> MIO0 is an output pin driving ‘0’
11 -> MIO0 is an output pin driving ‘1’
Read/Write
EEPROM PCMCIA
-
R
W
R/W
Reset
0000
00
W
R/W
00
Table 8: Multi Purpose I/O Configuration Register
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