MT9D131 Datasheet, PDF (94/132 Pages) ON Semiconductor – CMOS Digital Image Sensor

MT9D131: 1/3.2-Inch 2-Mp SOC Digital Image Sensor
Feature Description
This is a particularly strict requirement during binning because twice as many row oper-
ations are required per row and the column width is halved.
Table 26: Minimum Row Time Parameters
Parameter
ROW_TIME(MIN)
pointer_operations
Default / 2 ADC
Mode, No Binning
473 mclks
461 mclks
1 ADC Mode,
No Binning
488 mclks
= 244 pixclks
464 mclks
2 ADC Mode, Binning
931 mclks
1 ADC Mode, Binning
946 mclks = 473 pixclks
919 mclks
922 mclks
Context Switching
When the sensor is in the SOC bypass mode, R0xF2:0 is designed to enable easy
switching between sensor modes. Some key registers and bits in the sensor have two
physical register locations, called contexts. Bits 0, 1, and 3 of R0xF2:0 control which
context register context is currently in use. A “1” in a bit selects context B, while a “0”
selects context A for this parameter. The select bits can be used in any combination, but
by default are set up to allow easy switching between preview mode and full resolution
mode:
Context B (Default context)
R0xF2:0
= 0x000B
R0x05:0
= 0x015C
R0x06:0
= 0x0020
R0x20:0
= 0x0000
(Context B)
(Horizontal blanking, context B)
(Vertical Blanking, context B)
(2 ADCs, no column or row skip)
Description:
Full resolution UXGA (1,600 x 1,200) image at 15 fps
Context A (Alternate context, preview mode)
R0xF2:0
= 0x0000
(Context A)
R0x07:0
= 0x00AE
(Horizontal blanking, context A)
R0x08:0
= 0x0010
(Vertical blanking, context A)
R0x21:0
= 0x0490
(1 ADC, 2x column and row skip)
Description:
Half-resolution SVGA (800 x 600) image at 30 fps
The horizontal blanking and vertical blanking values for the two contexts are chosen so
that row time is preserved between contexts. This ensures that changing contexts does
not affect integration time. See Table 5, “Sensor Core Register Description,” on page 23
for more information.
Settings for skip, 1 ADC mode, and binning can be set separately for context B and
context A using R0x20:0 and R0x21:0, respectively. When these settings are referred to in
this document, the register is dependent on what context is set in R0xF2:0. For the
default (no bypass) mode, context switching is controlled by the sequencer (ID = 1)
driver.
MT9D131_DS Rev. J 5/15 EN
94
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