MT9D131 Datasheet, PDF (106/132 Pages) ON Semiconductor – CMOS Digital Image Sensor

MT9D131: 1/3.2-Inch 2-Mp SOC Digital Image Sensor
Start-Up and Usage
Hard Reset Sequence
After power-up, a hard reset is required. Assuming all supplies are stable, the assertion of
RESET_BAR (active LOW) sets the device in reset mode. The clock is required to be active
when RESET_BAR is released. Hence, leaving the input clock running during the reset
duration is recommended. After 24 clock cycles (EXTCLK), the two-wire serial interface
is ready to accept commands. Reset should not be activated while STANDBY is asserted.
A hard reset sequence to the camera can be activated by the following steps:
1. Wait for all power supplies to be stable and within specification.
2. Supply the sensor with an input clock.
3. Assert RESET_BAR (active LOW) for at least 1µs.
4. De-assert RESET_BAR (input clock must be running).
5. Wait 24 clock cycles before using the two-wire serial interface.
Refer to Figure 28 for the timing diagram.
Figure 28: Power On/Off Sequence
VDD, VDDQ,
VAA, VAAPIX
POWER UP
RESET (>1μs)
POWER
DOWN
RESET#
EXTCLK
SCLK/SDATA (SHIP)
24-EXTCLK
INACTIVE
INACTIVE
Notes:
STANDBY
1. For a safe RESET to occur, EXTCLK should be running during RESET with STANDBY LOW, as shown in
the sequence above.
2. After RESET_BAR is HIGH, wait 24 EXTCLK rising edges before the two-wire serial interface commu-
nication is initiated.
3. After the power-up sequence, the preview state is reached when the firmware variable seq.state (ID
= 1, Offset = 4) is equal to 3. This transition time varies depending on the input clock frequency and
scene conditions.
4. To go into the firmware standby state, go to capture mode (also known as context B), or execute the
firmware REFRESH/REFRESH_MODE commands after the power-up sequence (the preview state
[seq.state = 3] must be reached first).
MT9D131_DS Rev. J 5/15 EN
106
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