MT9D131 Datasheet, PDF (127/132 Pages) ON Semiconductor – CMOS Digital Image Sensor

MT9D131: 1/3.2-Inch 2-Mp SOC Digital Image Sensor
Appendix A: Two-Wire Serial Register Interface
Acknowledge Bit
The master generates the acknowledge clock pulse. The transmitter (which is the master
when writing, or the slave when reading) releases the data line, and the receiver indi-
cates an acknowledge bit by pulling the data line LOW during the acknowledge clock
pulse.
No-Acknowledge Bit
The no-acknowledge bit is generated when the data line is not pulled down by the
receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate
a read sequence.
Page Register
The MT9D131 two-wire serial interface and its associated protocols support an address
space of 256 16-bit locations. This address space is extended by a 3-bit page prefix, and
controlled through accesses to R0xF0:0.
The paging mechanism is intended to allow access to other sets of registers when the
sensor is embedded as part of a more complex integrated subsystem, for example, in an
SOC. All registers within the sensor core are accessible on page 0 (the default page).
Sample Write and Read Sequences
16-Bit Write Sequence
A typical write sequence for writing 16 bits to a register is shown in Figure 40. A start bit
given by the master starts the sequence, followed by the write address. The image sensor
then sends an acknowledge bit and expects the register address to come first, followed
by the 16-bit data. After each 8-bit transfer, the image sensor sends an acknowledge bit.
All 16 bits must be written before the register is updated. After 16 bits are transferred, the
register address is automatically incremented so that the next 16 bits are written to the
next register. The master stops writing by sending a start or stop bit.
Figure 40: WRITE Timing to R0x09:0—Value 0x0284
SCLK
SDATA
0xBA Address
Start
ACK
R0x09
ACK
0000 0010
ACK
1000 0100
Stop
ACK
16-Bit Read Sequence
A typical read sequence is shown in Figure 41 on page 128. First the master writes the
register address, as in a write sequence. Then a start bit and the read address specify that
a read is about to happen from the register. The master clocks out the register data, eight
bits at a time. The master sends an acknowledge bit after each 8-bit transfer. The register
address should be incremented after every 16 bits is transferred. The data transfer is
stopped when the master sends a no-acknowledge bit.
MT9D131_DS Rev. J 5/15 EN
127
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