MT9D131 Datasheet, PDF (125/132 Pages) ON Semiconductor – CMOS Digital Image Sensor

MT9D131: 1/3.2-Inch 2-Mp SOC Digital Image Sensor
Appendix A: Two-Wire Serial Register Interface
Appendix A: Two-Wire Serial Register Interface
This section describes the two-wire serial interface bus that can be used in any func-
tional sensor mode.
The two-wire serial interface bus enables R/W access to control and status registers
within the sensor core.
The interface protocol uses a master/slave model in which a master controls one or
more slave devices. The sensor acts as a slave device. The master generates a clock (SCLK)
that is an input to the sensor and used to synchronize transfers. The master is respon-
sible for driving a valid logic level on SCLK at all times. Data is transferred between the
master and the slave on a bidirectional signal (SDATA). Both the SDATA AND SCLK signal
are pulled up to VDD off-chip by a 1.5K resistor. Either the slave or master device can
drive the SDATA line low—the interface protocol determines which device is allowed to
drive the SDATA line at any given time.
Protocol
The two-wire serial interface bus defines the transmission codes as follows:
• a start bit
• the slave device 8-bit address
• a(an) (no) acknowledge bit
• an 8-bit message
• a stop bit
Sequence
A typical read or write sequence is executed as follows:
1. The master sends a start bit.
2. The master sends the 8-bit slave device address. The last bit of the address determines
if the request is a read or a write, where a “0” indicates a write and a “1” indicates a
read.
3. The slave device acknowledges receipt of the address by sending an acknowledge bit
to the master.
4. If the request is a write, the master then transfers the 8-bit register address, indicating
where the write takes place.
5. The slave sends an acknowledge bit, indicating that the register address has been
received.
6. The master then transfers the data, 8 bits at a time, with the slave sending an acknowl-
edge bit after each 8 bits.
The sensor core uses 16-bit data for its internal registers, thus requiring two 8-bit trans-
fers to write to one register. After 16 bits are transferred, the register address is automati-
cally incremented so that the next 16 bits are written to the next register address. The
master stops writing by sending a start or stop bit.
A typical read sequence is executed as follows.
1. The master sends the write-mode slave address and 8-bit register address, just as in
the write request.
2. The master then sends a start bit and the read-mode slave address, and clocks out the
register data, 8 bits at a time.
3. The master sends an acknowledge bit after each 8-bit transfer. The register address is
auto-incremented after every 16 bits is transferred.
4. The data transfer is stopped when the master sends a no-acknowledge bit.
MT9D131_DS Rev. J 5/15 EN
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