NCN8026A_16 Datasheet, PDF (9/15 Pages) ON Semiconductor – Compact Low Power Smart Card Interface IC

NCN8026A
SMART CARD INTERFACE SECTION CI/O, CAUX1, CAUX2, CCLK, CRST, PRES, PRES (V_DD = 3.3 V; V_DDP = 5 V; T_amb = 25°C;
F_CLKIN = 5 MHz)
Symbol
Rating
Min
Typ
Max
Unit
PRES, PRES
Low level input leakage current, V_IH = V_DD
|I_IH|
PRES
PRES
High level input leakage current, V_IL = 0 V
|I_IL|
PRES
PRES
mA
0.2
2.0
1.0
1.0
0.2
2.0
T_debounce
I_CI/O
I_CCLK
I_CRST
T_act
T5
Debounce time PRES and PRES (Note 7)
CI/O, CAUX1, CAUX2 current limitation, CVCC enabled
CCLK current limitation
CRST current limitation
Activation Time (Note 7)
RSTIN time control (Figure 5) (Note 7)
5
8
12
ms
−
−
15
mA
−
−
70
mA
−
−
20
mA
30
−
100
ms
200
240
280
ms
T_deact Deactivation Time (Note 7)
7. Guaranteed by design and characterization.
30
−
250
ms
POWER SUPPLY
The NCN8026A smart card interface has two power
supplies: V_DD and V_DDP.
V_DD is common to the system controller and the interface.
The applied V_DD range can go from 1.6 V up to 5.5 V. If V_DD
goes below 1.45 V typical (UVLO_VDD) a power−down
sequence is automatically performed. In that case the
interrupt (INT) pin is set Low.
A Low Drop−Out (LDO) and low noise regulator is used
to provide the 1.8 V, 3 V or 5 V power supply voltage
(CVCC) to the card. V_DDP is the LDO’s input voltage.
CVCC is the LDO output. The typical distributed reservoir
output capacitor connected to CVCC is 100 nF + 220 nF. The
capacitor of 100 nF is connected as close as possible to the
CVCC’s pin and the 220 nF one as close as possible to the
card connector C1 pin. Both feature very low ESR values
(lower than 50 mW). The decoupling capacitors on V_DD and
V_DDP respectively 100 nF and 10 mF + 100 nF have also to
be connected close to the respective IC pins.
The CVCC pin can source up to 70 mA at 1.8 V, 3 V and
5 V continuously over the V_DDP range (see corresponding
specification table), the absolute maximum current being
internally limited below 150 mA (Typical at 120 mA).
The card V_CC voltage (CVCC) can be programmed with
the pins VSEL0 and VSEL1 and according to the below table:
Table 1. CVCC PROGRAMMING
VSEL0
VSEL1
CVCC
0
0
3.0 V
0
1
5.0 V
1
0
3.0 V
1
1
1.8 V
VSEL0 can be used to select the CVCC programming
mode which can be 5V/3V (VSEL0 connected to Ground)
or 1.8V/3V (VSEL0 connected to V_DD). VSEL0 and
VSEL1 are usually programmed before activating the smart
card interface that is when CMDVCC is High.
There’s no specific sequence for applying V_DD or V_DDP.
They can be applied to the interface in any sequence. After
powering the device INT pin remains Low until a card is
inserted.
SUPPLY VOLTAGE MONITORING
The supply voltage monitoring block includes the
Power−On Reset (POR) circuitry and the under−voltage
lockout (UVLO) detection (V_DD voltage dropout
detection). PORADJ pin allows the user, according to the
considered application, to adjust the V_DD UVLO threshold.
If not used PORADJ pin is connected to Ground
(recommended even if it may be left unconnected).
The input supply voltage is continuously monitored to
prevent under voltage operation. At power up, the system
initializes the internal logic during POR timing and no further
signal can be provided or supported during this period.
The system is ready to operate when the input voltage has
reached the minimum V_DD. Considering this, the
NCN8026A will detect an Under−Voltage situation when
the input supply voltage will drop below 1.45 V typical.
When V_DD goes down below the UVLO falling threshold a
deactivation sequence is performed.
The device is inactive during power−on and power−off of
the V_DD supply (8 ms reset pulse).
PORADJ pin is used to modify the UVLO threshold
according to the below relationship considering an external
resistor divider R1 / R2 (see block diagram Figure 1):
UVLO
+
R1 ) R2
R2
V_POR
(eq. 1)
If PORADJ is connected to Ground the V_DD UVLO
threshold (V_DD falling) is typically 1.45 V. In some cases it
can be interesting to adjust this threshold at a higher value
and by the way increase the V_DD supply dropout detection
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