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NCN8026A_16 Datasheet, PDF (8/15 Pages) ON Semiconductor – Compact Low Power Smart Card Interface IC
NCN8026A
SMART CARD INTERFACE SECTION CI/O, CAUX1, CAUX2, CCLK, CRST, PRES, PRES (VDD = 3.3 V; VDDP = 5 V; Tamb = 25°C;
FCLKIN = 5 MHz)
Symbol
Rating
Min
Typ
Max
Unit
CRST @ CVCC = 1.8 V, 3.0 V, 5.0 V
VOH
VOL
Output RESET VOH @ Irst = −200 mA
Output RESET VOL @ Irst = 200 mA
0.9 x CVCC
−
CVCC
V
0
−
0.20
V
tR
Output RESET VOH @ Irst = −20 mA
0
0.4
V
tF
Output RESET VOL @ Irst = 20 mA
CVCC − 0.4
CVCC
V
tR/F
Output RESET Rise time @ Cout = 100 pF (Note 7)
−
−
100
ns
td
Output RESET Fall time @ Cout = 100 pF (Note 7)
−
−
100
ns
Output Rise/Fall times @ CVCC = 1.8 V & Cout = 100 pF (Note 7)
−
−
200
ns
RSTIN to CRST delay − Reset enabled (Note 7)
−
−
2
ms
CCLK @ CVCC = 1.8 V, 3.0 V or 5.0 V
FCRDCLK Output Frequency (Note 7)
VOH
VOL
Output CCLK VOH @ Iclk = −200 mA
Output CCLK VOL @ Iclk = 200 mA
Output CCLK VOH @ Iclk = −70 mA
FDC
Output CCLK VOL @ Iclk = 70 mA
Output Duty Cycle (Note 7)
trills
tulsa Rise & Fall time
Output CCLK Rise time @ Cout = 33 pF (Note 7)
SR
Output CCLK Fall time @ Cout = 33 pF (Note 7)
Slew Rate @ Cout = 33 pF (CVCC = 3.0 V or 5.0 V) (Note 7)
CAUX1, CAUX2, CI/O @ CVCC = 1.8 V, 3.0 V, 5.0 V
−
−
0.9 x CVCC
−
0
−
0
CVCC − 0.4
45
−
−
−
−
−
0.2
−
27
CVCC
+0.2
0.4
CVCC
55
16
16
−
MHz
V
V
V
V
%
ns
ns
V/ns
VIH
Input Voltage High Level
1.8 V Mode
3.0 V Mode
5.0 V Mode
VIL
Input Voltage Low Level
1.8 V mode
3.0 V and 5.0 V modes
0.7xVCC
1.6
1.8
−0.30
−0.30
− CVCC + 0.3 V
−
CVCC+ 0.3
V
− CVCC + 0.3 V
−
0.50
V
−
0.80
V
|IIL|
|IIH|
VOH
VOL
tRi / Fi
tRo / Fo
Low Level Input current VIL = 0 V
High Level Input current VIH = CVCC
Output VOH
@ IOH = no DC load
@ IOH = −40 mA for CVCC = 3.0 V and 5.0 V
@ IOH = −20 mA for CVCC = 1.8 V
@ IOH ≥ −15 mA
Output VOL
@ IOL = 1 mA, VIL = 0 V
@ IOL ≥ +15 mA
Input Rising/Falling times (Note 7)
−
600
mA
−
10
mA
0.9xCVCC
0.75xCVCC
0.75xCVCC
0
0
VCC − 0.4
−
CVCC + 0.1 V
− CVCC + 0.1 V
− CVCC + 0.1
−
0.4
V
−
0.30
ms
−
VCC
ms
−
1.2
Output Rising/Falling times / Cout = 80 pF (Note 7)
−
Fbidi Maximum data rate through bidirectional I/O, AUX1 & AUX2 channels (Note 7)
−
RPU CAUX1, CAUX2, CI/O Pull− Up Resistor
8
tIO
Propagation delay IOuc −> CI/O and CI/O −> IOuc (falling edge) (Note 7)
−
tpu Active pull−up pulse width buffers I/O, AUX1 and AUX2 (Note 7)
−
Cin
Input Capacitance on data channels (Note 7)
PRES, PRES
VIH
Card Presence Voltage High Level
VIL
Card Presence Voltage Low Level
−
0.7 x VDD
−0.3
−
0.1
−
1
MHz
11
16
kW
−
200
ns
−
200
ns
−
10
pF
V
−
VDD + 0.3
−
0.3 x VDD
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