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NCN8026A_16 Datasheet, PDF (8/15 Pages) ON Semiconductor – Compact Low Power Smart Card Interface IC | |||
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NCN8026A
SMART CARD INTERFACE SECTION CI/O, CAUX1, CAUX2, CCLK, CRST, PRES, PRES (VDD = 3.3 V; VDDP = 5 V; Tamb = 25°C;
FCLKIN = 5 MHz)
Symbol
Rating
Min
Typ
Max
Unit
CRST @ CVCC = 1.8 V, 3.0 V, 5.0 V
VOH
VOL
Output RESET VOH @ Irst = â200 mA
Output RESET VOL @ Irst = 200 mA
0.9 x CVCC
â
CVCC
V
0
â
0.20
V
tR
Output RESET VOH @ Irst = â20 mA
0
0.4
V
tF
Output RESET VOL @ Irst = 20 mA
CVCC â 0.4
CVCC
V
tR/F
Output RESET Rise time @ Cout = 100 pF (Note 7)
â
â
100
ns
td
Output RESET Fall time @ Cout = 100 pF (Note 7)
â
â
100
ns
Output Rise/Fall times @ CVCC = 1.8 V & Cout = 100 pF (Note 7)
â
â
200
ns
RSTIN to CRST delay â Reset enabled (Note 7)
â
â
2
ms
CCLK @ CVCC = 1.8 V, 3.0 V or 5.0 V
FCRDCLK Output Frequency (Note 7)
VOH
VOL
Output CCLK VOH @ Iclk = â200 mA
Output CCLK VOL @ Iclk = 200 mA
Output CCLK VOH @ Iclk = â70 mA
FDC
Output CCLK VOL @ Iclk = 70 mA
Output Duty Cycle (Note 7)
trills
tulsa Rise & Fall time
Output CCLK Rise time @ Cout = 33 pF (Note 7)
SR
Output CCLK Fall time @ Cout = 33 pF (Note 7)
Slew Rate @ Cout = 33 pF (CVCC = 3.0 V or 5.0 V) (Note 7)
CAUX1, CAUX2, CI/O @ CVCC = 1.8 V, 3.0 V, 5.0 V
â
â
0.9 x CVCC
â
0
â
0
CVCC â 0.4
45
â
â
â
â
â
0.2
â
27
CVCC
+0.2
0.4
CVCC
55
16
16
â
MHz
V
V
V
V
%
ns
ns
V/ns
VIH
Input Voltage High Level
1.8 V Mode
3.0 V Mode
5.0 V Mode
VIL
Input Voltage Low Level
1.8 V mode
3.0 V and 5.0 V modes
0.7xVCC
1.6
1.8
â0.30
â0.30
â CVCC + 0.3 V
â
CVCC+ 0.3
V
â CVCC + 0.3 V
â
0.50
V
â
0.80
V
|IIL|
|IIH|
VOH
VOL
tRi / Fi
tRo / Fo
Low Level Input current VIL = 0 V
High Level Input current VIH = CVCC
Output VOH
@ IOH = no DC load
@ IOH = â40 mA for CVCC = 3.0 V and 5.0 V
@ IOH = â20 mA for CVCC = 1.8 V
@ IOH ⥠â15 mA
Output VOL
@ IOL = 1 mA, VIL = 0 V
@ IOL ⥠+15 mA
Input Rising/Falling times (Note 7)
â
600
mA
â
10
mA
0.9xCVCC
0.75xCVCC
0.75xCVCC
0
0
VCC â 0.4
â
CVCC + 0.1 V
â CVCC + 0.1 V
â CVCC + 0.1
â
0.4
V
â
0.30
ms
â
VCC
ms
â
1.2
Output Rising/Falling times / Cout = 80 pF (Note 7)
â
Fbidi Maximum data rate through bidirectional I/O, AUX1 & AUX2 channels (Note 7)
â
RPU CAUX1, CAUX2, CI/O Pullâ Up Resistor
8
tIO
Propagation delay IOuc â> CI/O and CI/O â> IOuc (falling edge) (Note 7)
â
tpu Active pullâup pulse width buffers I/O, AUX1 and AUX2 (Note 7)
â
Cin
Input Capacitance on data channels (Note 7)
PRES, PRES
VIH
Card Presence Voltage High Level
VIL
Card Presence Voltage Low Level
â
0.7 x VDD
â0.3
â
0.1
â
1
MHz
11
16
kW
â
200
ns
â
200
ns
â
10
pF
V
â
VDD + 0.3
â
0.3 x VDD
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