NCN8026A_16 Datasheet, PDF (11/15 Pages) ON Semiconductor – Compact Low Power Smart Card Interface IC

NCN8026A
The clock can also be applied to the card using a RSTIN
mode allowing controlling the clock starting by setting
RSTIN Low (Figure 4). Before running the activation
sequence, that is before setting Low CMDVCC RSTIN is set
High. The following sequence is applied:
− The Smart Card Interface is enable by setting
CMDVCC LOW (RSTIN is High).
− Between t2 (Figure 4) and t5 = 240 ms, RSTIN is reset
to LOW and CCLK will start precisely at this moment
allowing a precise count of clock cycles before toggling
CRST Low to High for ATR (Answer To Reset)
request.
− CRST remains LOW until 240 ms; after t5 = 240 ms
CRST is enabled and is the copy of RSTIN which has
no more control on the clock.
CMDVCC
If controlling the clock with RSTIN is not necessary
(Normal Mode), then CMDVCC can be set LOW with
RSTIN LOW. In that case, CLK will start minimum 2 ms
after the transition on I/O (Figure 5), and to obtain an ATR,
CRST can be set High by RSTIN also about 2 ms after the
clock channel activation (T_act).
The internal activation sequence activates the different
channels according to a specific hardware built−in
sequencing internally defined but at the end the actual
activation sequencing is the responsibility of the application
software and can be redefined by the micro−controller to
comply with the different standards and the different ways
the standards manage this activation (for example light
differences exist between the EMV and the ISO7816
standards).
CVCC
ATR
CIO
CCLK
RSTIN
CRST
t0
t1 t2 t4
t5
~240 ms
Figure 4. Activation Sequence − RSTIN Mode (RSTIN Starting High)
CMDVCC
CVCC
CIO
ATR
CCLK
RSTIN
CRST
t0
t1 t2 t3
t4
T_act
Figure 5. Activation Sequence − Normal Mode
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