CAV25640 Datasheet, PDF (9/14 Pages) ON Semiconductor – 64-Kb SPI Serial CMOS EEPROM

CAV25640
READ OPERATIONS
Read from Memory Array
To read from memory, the host sends a READ instruction
followed by a 16−bit address (see Table 11 for the number
of significant address bits).
After receiving the last address bit, the CAV25640 will
respond by shifting out data on the SO pin (as shown in
Figure 9). Sequentially stored data can be read out by simply
continuing to run the clock. The internal address pointer is
automatically incremented to the next higher address as data
is shifted out. After reaching the highest memory address,
the address counter “rolls over” to the lowest memory
address, and the read cycle can be continued indefinitely.
The read operation is terminated by taking CS high.
Read Status Register
To read the status register, the host simply sends a RDSR
command. After receiving the last bit of the command, the
CAV25640 will shift out the contents of the status register on
the SO pin (Figure 10). The status register may be read at
any time, including during an internal write cycle. While the
internal write cycle is in progress, the RDSR command will
output the contents of the status register.
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30
OPCODE
BYTE ADDRESS*
SI
0 0 0 0 0 0 1 1 ^AN
A₀
HIGH IMPEDANCE
SO
Dashed Line = mode (1, 1)
* Please check the Byte Address Table (Table 11)
Figure 9. READ Timing
DATA OUT
765432 10
MSB
CS
SCK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
OPCODE
SI
0
0
0
0
0
1
01
HIGH IMPEDANCE
SO
DATA OUT
7
6
5
4
32
10
Dashed Line = mode (1, 1)
MSB
Figure 10. RDSR Timing
http://onsemi.com
9