CAV25640 Datasheet, PDF (3/14 Pages) ON Semiconductor – 64-Kb SPI Serial CMOS EEPROM

CAV25640
Table 4. PIN CAPACITANCE (T_A = 25°C, f = 1.0 MHz, V_CC = +5.0 V) (Note 2)
Symbol
Test
Conditions
C_OUT
C_IN
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
V_OUT = 0 V
V_IN = 0 V
Min
Typ
Table 5. A.C. CHARACTERISTICS (T_A = −40°C to +125°C) (Note 4)
V_CC = 2.5 V − 5.5 V
Symbol
Parameter
Min
Max
f_SCK
Clock Frequency
DC
10
t_SU
Data Setup Time
10
t_H
Data Hold Time
10
t_WH
SCK High Time
40
t_WL
SCK Low Time
40
t_LZ
HOLD to Output Low Z
25
t_RI (Note 5)
Input Rise Time
2
t_FI (Note 5)
Input Fall Time
2
t_HD
HOLD Setup Time
0
t_CD
HOLD Hold Time
10
t_V
Output Valid from Clock Low
35
t_HO
Output Hold Time
0
t_DIS
Output Disable Time
20
t_HZ
HOLD to Output High Z
25
t_CS
CS High Time
40
t_CSS
CS Setup Time
30
t_CSH
CS Hold Time
30
t_CNS
CS Inactive Setup Time
20
t_CNH
CS Inactive Hold Time
20
t_WPS
WP Setup Time
10
t_WPH
WP Hold Time
10
t_WC (Note 6)
Write Cycle Time
5
4. AC Test Conditions:
Input Pulse Voltages: 0.3 V_CC to 0.7 V_CC
Input rise and fall times: ≤ 10 ns
Input and output reference voltages: 0.5 V_CC
Output load: current source I_{OL max}/I_{OH max}; C_L = 30 pF
5. This parameter is tested initially and after a design or process change that affects the parameter.
6. t_WC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
Table 6. POWER−UP TIMING (Notes 5, 7)
Symbol
Parameter
Max
t_PUR
Power−up to Read Operation
1
t_PUW
Power−up to Write Operation
1
7. t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified operation can be initiated.
Max
Units
8
pF
8
pF
Units
MHz
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Units
ms
ms
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