CAT5401WI-25 Datasheet, PDF (9/15 Pages) ON Semiconductor – Quad Digitally Programmable Potentiometers with 64 Taps and SPI Interface

CAT5401
The basic sequence of the three byte instructions is
illustrated in Figure 4. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper.
The response of the wiper to this action will be
delayed by t_WRL. A transfer from the WCR (current
wiper position), to a Data Register is a write to non-
volatile memory and takes a minimum of t_WR to
complete. The transfer can occur between one of the
four potentiometers and one of its associated
registers; or the transfer can occur between all
potentiometers and one associated register.
Four instructions require a two-byte sequence to
complete, as illustrated in Figure 3. These instructions
transfer data between the host/processor and the
CAT5401; either between the host and one of the data
registers or directly between the host and the Wiper
Control Register. These instructions are:
— XFR Data Register to Wiper Control Register
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
— XFR Wiper Control Register to Data Register
This transfers the contents of the specified Wiper
Control Register to the specified associated Data
Register.
— Gang XFR Data Register to Wiper Control
Register
This transfers the contents of all specified Data
Registers to the associated Wiper Control
Registers.
— Gang XFR Wiper Counter Register to Data
Register
This transfers the contents of all Wiper Control
Registers to the specified associated Data
Registers.
Increment/Decrement Command
The final command is Increment/Decrement (Figure
5). The Increment/Decrement command is different
from the other commands. Once the command is
issued the master can clock the selected wiper up
and/or down in one segment steps; thereby providing
a fine tuning capability to the host. For each SCK
clock pulse (t_HIGH) while SI is HIGH, the selected wiper
will move one resistor segment towards the R_H
terminal. Similarly, for each SCK clock pulse while SI
is LOW, the selected wiper will move one resistor
segment towards the R_L terminal.
See Instructions format for more detail.
Figure 3. Two-Byte Instruction Sequence
SI
0101 00
ID3 ID2 ID1 ID0 _A3 A2 A1 A0 _{I3 I2 I1 I0 R1 R0 P1 P0}
Device ID
Internal
Address
Instruction
Opcode
Register Pot/WCR
Address Address
Figure 4. Three-Byte Instruction Sequence
SI
0 10100
ID3 ID2 ID1 ID0 A3 A2 A1 A0 ^I3 I2 ^I1 I0 R1 R0 ^{P1 P0 D7 D6 D5 D4 D3 D2 D1 D0}
Device ID
Internal
Address
Instruction
Opcode
Data Pot/WCR
Register Address
Address
WCR[7:0]
or
Data Register D[7:0]
Figure 5. Increment/Decrement Instruction Sequence
SI
010100
ID3 ID2 ID1 ID0 A3 A2 A1 A0 _{I3 I2} I1 _{I0 R1 R0 P1 P0 I I}
ID
D
Device ID
Internal
Address
NN
NE
E
Instruction Data Pot/WCR C C
CC
C
Opcode
Register ^{Address 1 2}
n1
n
Address
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9
Characteristics subject to change without notice
Doc. No. MD-2012 Rev. I