CAT5401WI-25 Datasheet, PDF (1/15 Pages) ON Semiconductor – Quad Digitally Programmable Potentiometers with 64 Taps and SPI Interface

CAT5401
Quad Digitally Programmable Potentiometers
(DPP™) with 64 Taps and SPI Interface
FEATURES
„ Four linear taper digitally programmable
potentiometers
„ 64 resistor taps per potentiometer
„ End to end resistance 2.5kΩ, 10kΩ, 50kΩ or
100kΩ
„ Potentiometer control and memory access via
SPI interface: Mode (0, 0) and (1, 1)
„ Low wiper resistance, typically 100Ω
„ Nonvolatile memory storage for up to four
wiper settings for each potentiometer
„ Automatic recall of saved wiper settings at
power up
„ 2.5 to 6.0 volt operation
„ Standby current less than 1µA
„ 1,000,000 nonvolatile WRITE cycles
„ 100 year nonvolatile memory data retention
„ 24-lead SOIC and 24-lead TSSOP
„ Industrial temperature range
For Ordering Information details, see page 14.
DESCRIPTION
The CAT5401 is four Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists
of a series of 63 resistive elements connected
between two externally accessible end points. The tap
points between each resistive element are connected
to the wiper outputs with CMOS switches. A separate
6-bit control register (WCR) independently controls
the wiper tap switches for each DPP. Associated with
each wiper control register are four 6-bit non-volatile
memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or
any of the non-volatile data registers is via a SPI serial
bus. On power-up, the contents of the first data
register (DR0) for each of the four potentiometers is
automatically loaded into its respective wiper control
register.
The CAT5401 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
PIN CONFIGURATION
SOIC Package (W)
TSSOP Package (Y)
VCC
RL0
RH0
RW0
CS
WP
SI
A1
RL1
RH1
RW1
GND
1
24
2
23
3
22
4
21
5
20
6 _CAT 19
7 ⁵⁴⁰¹ 18
8
17
9
16
10
15
11
14
12
13
NC
SI
RL3
A1
RH3 RL1
RW3 RH1
A0 RW1
SO GND
HOLD NC
SCK RW2
RL2 RH2
RH2 RL2
RW2 SCK
NC HOLD
1
24
2
23
3
22
4
21
5
20
6 _CAT 19
7 ⁵⁴⁰¹ 18
8
17
9
16
10
15
11
14
12
13
WP
CS
RW0
RH0
RL0
VCC
NC
RL3
RH3
RW3
A0
SO
FUNCTIONAL DIAGRAM
CS
SCK
SI
SO
WP
A₀
A₁
R_H0
R_H1
R_H2
R_H3
SPI BUS
WIPER CONTROL
INTERFACE
REGISTERS
R_W0
R_W1
NONVOLATILE
R_W2
CONTROL LOGIC
DATA
REGISTERS
R_W3
R_L0
R_L1
R_L2
R_L3
© 2008 SCILLC. All rights reserved.
1
Characteristics subject to change without notice
Doc. No. MD-2012 Rev. I