CAT5401WI-25 Datasheet, PDF (3/15 Pages) ON Semiconductor – Quad Digitally Programmable Potentiometers with 64 Taps and SPI Interface

CAT5401
SERIAL BUS PROTOCOL
The CAT5041 supports the SPI bus data transmission
protocol. The synchronous Serial Peripheral Interface
(SPI) helps the CAT5401 to interface directly with
many of today's popular microcontrollers. The
CAT5041 contains an 8-bit instruction register. The
instruction set and the operation codes are detailed in
the instruction set table 3.
After the device is selected with ^{¯C¯S¯} going low the first
byte will be received. The part is accessed via the SI
pin, with data being clocked in on the rising edge of
SCK. The first byte contains one of the six op-codes
that define the operation to be performed.
DEVICE OPERATION
The CAT5401 is four resistor arrays integrated with
SPI serial interface logic, four 6-bit wiper control
registers and sixteen 6-bit, non-volatile memory data
registers. Each resistor array contains 63 separate
resistive elements connected in series. The physical
ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R_H and R_L).
R_H and R_L are symmetrical and may be interchanged.
The tap positions between and at the ends of the
series resistors are connected to the output wiper
terminals (R_W) by a CMOS transistor switch. Only one
tap point for each potentiometer is connected to its
wiper terminal at a time and is determined by the
value of the wiper control register. Data can be read
or written to the wiper control registers or the non-
volatile memory data registers via the SPI bus.
Additional instructions allows data to be transferred
between the wiper control registers and each
respective potentiometer's non-volatile data registers.
Also, the device can be instructed to operate in an
"increment/decrement" mode.
© 2008 SCILLC. All rights reserved.
3
Characteristics subject to change without notice
Doc. No. MD-2012 Rev. I