AMIS-39101 Datasheet, PDF (9/12 Pages) AMI SEMICONDUCTOR – Octal High-Side Driver with Protection

AMIS−39101
Table 10. POWER LOSS
VDDN
VS
Possible Case
0
0
System stopped
0
1
Start case or sleeping mode with missing VDDN
1
0
Missing VS supply
VDDN normally present
1
1
System functional
Action
Nothing
Eight switches in the off−state
Power down consumption on VS
Eight switches in the off−state
Normal consumption on VDDN
Nominal functionality
Serial Interface
The serial interface is used to allow an external microcontroller (MCU) to communicate with the device. The AMIS−39101
always acts as a slave and it can’t initiate any transmission.
Serial Interface Transfer Format and Pin Signals
The serial interface block diagram and timing
characteristics are shown in Figures 6 and 7.
During a serial interface transfer, data is simultaneously
sent to and received from the device. A serial clock line
(CLK) synchronizes shifting and sampling of the
information on the two serial data lines (DIN and DOUT).
DOUT signal is the output from the AMIS−39101 to the
external MCU and DIN signal is the input from the MCU to
the AMIS−39101. The WR−pin selects the AMIS−39101 for
communication and can also be used as a chip select (CS) in
a multiple−slave system. The WR−pin is active low. If
AMIS−39101 is not selected, DOUT is in high impedance
state and it does not interfere with serial interface bus
activities. Since AMIS−39101 always shifts data out on the
rising edge and samples the input data also on the rising edge
of the CLK signal, the MCU serial interface port must be
configured to match this operation. Serial interface clock
idles high between the transferred bytes.
The diagram in Figure 7 represents the serial interface
timing diagram for 8−bit communication.
Communication starts with a falling edge on the WR−pin
which latches the status of the diagnostic register into the
serial interface output register. Subsequently, the CMD_x
bits – representing the newly requested driver status – are
shifted into the input register and simultaneously, the
DIAG_x bits – representing the actual output status – are
shifted out. The bits are shifted with x = 1 first and ending
with x = 8. At the rising edge of the WR−pin, the data in the
input register is latched into the command register and all
drivers are simultaneously switching to the newly requested
status. Serial interface communication is ended.
In case the serial interface master does only support 16−bit
communication, then the master must first send 8 clock
pulses with dummy DIN data and ignoring the DOUT data.
For the next 8 clock pulses the above description can be
applied.
The required timing for serial to peripheral interface is
shown in Table 11.
Table 11. DIGITAL CHARACTERISTICS
Symbol
Description
T_CLK
Maximum applied clock frequency on CLK input
T_DATA_ready
Time between falling edge on WR and first bit of data ready on DOUT output
(driver going from HZ state to output of first diagnostic bit)
T_CLK_first
First clock edge from falling edge on WR
T_setup (Note 12) Setup time on DIN
T_hold (Note 12) Hold time on DIN
T_DATA_next
Time between rising edge on CLK and next bit ready on DOUT (capa on DOUT
is 30 pF max.)
T_serial
interface_END
Time between last CLK edge and WR rising edge
T_risefall
Rise and fall time of all applied signals (maximum loading capacitance is 30 pF)
T_WR
Time between two rising edge on WR (repetition of the same command)
12. Guaranteed by design
Min. Max. Unit
500
kHz
2
ms
3
ms
20
ns
20
ns
100
ns
1
ms
5
20
ns
300
ms
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