SA571 Datasheet, PDF (8/11 Pages) NXP Semiconductors – Compandor

SA571
Variable Gain Cell
Figure 12 is a diagram of the variable gain cell. This is a
linearized two−quadrant transconductance multiplier. Q₁,
Q₂ and the op amp provide a predistorted drive signal for the
gain control pair, Q₃ and Q₄. The gain is controlled by I_G and
a current mirror provides the output current.
V+
I₁
140mA
−
+
R₂
20k
Q₁
Q₂
V_IN
I_IN
Q₃ Q₄
I₂ (= 2I₁)
I_G
280mA
V−
NOTE:
I_OUT
+
I_G
I₁
I_IN
+
I_G V_IN
I₂ R₂
Figure 12. Simplified DG Cell Schematic
The op amp maintains the base and collector of Q₁ at
ground potential (V_REF) by controlling the base of Q₂. The
input current I_IN (= V_IN/R₂) is thus forced to flow through
Q₁ along with the current I₁, so I_C1 = I₁ + I_IN. Since I₂ has
been set at twice the value of I₁, the current through Q₂ is:
I₂ − (I₁ + I_IN) = I₁ − I_IN = I_C2.
The op amp has thus forced a linear current swing between
Q₁ and Q₂ by providing the proper drive to the base of Q₂.
This drive signal will be linear for small signals, but very
non−linear for large signals, since it is compensating for the
non−linearity of the differential pair, Q₁ and Q₂, under large
signal conditions.
The key to the circuit is that this same predistorted drive
signal is applied to the gain control pair, Q₃ and Q₄. When
two differential pairs of transistors have the same signal
applied, their collector current ratios will be identical
regardless of the magnitude of the currents. This gives us:
I_C1
I_C2
+
I_C4
I_C3
+
I₁ ) I_IN
I₁ * I_IN
plus the relationships I_G = I_C3 + I_C4 and I_OUT = I_C4 − I_C3 will
yield the multiplier transfer function,
I_OUT
+
I_G
I₁
I_IN
+
V_IN I_G
R₂ I₁
This equation is linear and temperature−insensitive, but it
assumes ideal transistors.
If the transistors are not perfectly matched, a parabolic,
non−linearity is generated, which results in second
harmonic distortion. Figure 13 gives an indication of the
magnitude of the distortion caused by a given input level and
offset voltage. The distortion is linearly proportional to the
magnitude of the offset and the input level. Saturation of the
gain cell occurs at a +8 dBm level. At a nominal operating
level of 0 dBm, a 1.0 mV offset will yield 0.34% of second
harmonic distortion. Most circuits are somewhat better than
this, which means our overall offsets are typically about mV.
The distortion is not affected by the magnitude of the gain
control current, and it does not increase as the gain is
changed. This second harmonic distortion could be
eliminated by making perfect transistors, but since that
would be difficult, we have had to resort to other methods.
A trim pin has been provided to allow trimming of the
internal offsets to zero, which effectively eliminated second
harmonic distortion. Figure 14 shows the simple trim
network required.
4
3
4mV
2
3mV
2mV
1
1mV
.34
−6 0
+6
INPUT LEVEL (dBm)
Figure 13. DG Cell Distortion vs. Offset Voltage
V_CC
6.2kW
To THD Trim
≈200pF
R
3.6V
20kW
Figure 14. THD Trim Network
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