SA571 Datasheet, PDF (5/11 Pages) NXP Semiconductors – Compandor

SA571
INTRODUCTION
Much interest has been expressed in high performance
electronic gain control circuits. For non−critical
applications, an integrated circuit operational
transconductance amplifier can be used, but when
high−performance is required, one has to resort to complex
discrete circuitry with many expensive, well−matched
components. This paper describes an inexpensive integrated
circuit, the SA571 Compandor, which offers a pair of high
performance gain control circuits featuring low distortion
(<0.1%), high signal−to−noise ratio (90 dB), and wide
dynamic range (110 dB).
Circuit Background
The SA571 Compandor was originally designed to satisfy
the requirements of the telephone system. When several
telephone channels are multiplexed onto a common line, the
resulting signal−to−noise ratio is poor and companding is
used to allow a wider dynamic range to be passed through
the channel. Figure 4 graphically shows what a compandor
can do for the signal−to−noise ratio of a restricted dynamic
range channel. The input level range of +20 to −80 dB is
shown undergoing a 2−to−1 compression where a 2.0 dB
input level change is compressed into a 1.0 dB output level
change by the compressor. The original 100 dB of dynamic
range is thus compressed to a 50 dB range for transmission
through a restricted dynamic range channel. A
complementary expansion on the receiving end restores the
original signal levels and reduces the channel noise by as
much as 45 dB.
The significant circuits in a compressor or expander are
the rectifier and the gain control element. The phone system
requires a simple full−wave averaging rectifier with good
accuracy, since the rectifier accuracy determines the (input)
output level tracking accuracy. The gain cell determines the
distortion and noise characteristics, and the phone system
specifications here are very loose. These specs could have
been met with a simple Operational Transconductance
Multiplier, or OTA, but the gain of an OTA is proportional
to temperature and this is very undesirable. Therefore, a
linearized transconductance multiplier was designed which
is insensitive to temperature and offers low noise and low
distortion performance. These features make the circuit
useful in audio and data systems as well as in
telecommunications systems.
Basic Hook−up and Operation
Figure 5 shows the block diagram of one half of the chip,
(there are two identical channels on the IC). The full−wave
averaging rectifier provides a gain control current, I_G, for the
variable gain (DG) cell. The output of the DG cell is a current
which is fed to the summing node of the operational
amplifier. Resistors are provided to establish circuit gain and
set the output DC bias.
The circuit is intended for use in single power supply
systems, so the internal summing nodes must be biased at
some voltage above ground. An internal band gap voltage
reference provides a very stable, low noise 1.8 V reference
denoted V_REF. The non−inverting input of the op amp is tied
to V_REF, and the summing nodes of the rectifier and DG cell
(located at the right of R₁ and R₂) have the same potential.
The THD trim pin is also at the V_REF potential.
INPUT
LEVEL
+20
0dB
OUTPUT
LEVEL
−20
0dB
−40
−40
NOISE
−80
−80
Figure 4. Restricted Dynamic Range Channel
THD TRIM
R₃ INV_IN
G_IN
R₂
3,14 _20kW
RECT_{IN R1}
8,9
R₃
5,12
6,11
20kW
DG
IG
R₄
30kW
−
V_REF
+
1.8V
OUTPUT
7,10
2,15 ^10kW
1,16
V_CC PIN 13
GND PIN 4
C_RECT
Figure 5. Chip Block Diagram (1 of 2 Channels)
http://onsemi.com
5