N24C02 Datasheet, PDF (8/10 Pages) ON Semiconductor – 2-Kb, 4-Kb, 8-Kb and 16-Kb I2C CMOS Serial EEPROM

N24C02, N24C04, N24C08, N24C16
READ OPERATIONS
Immediate Read
Upon receiving a Slave address with the R/W bit set to ‘1’,
the N24Cxx will interpret this as a request for data residing
at the current byte address in memory. The N24Cxx will
acknowledge the Slave address, will immediately shift out
the data residing at the current address, and will then wait for
the Master to respond. If the Master does not acknowledge
the data (NoACK) and then follows up with a STOP
condition (Figure 10), the N24Cxx returns to Standby mode.
Selective Read
Selective Read operations allow the Master device to
select at random any memory location for a read operation.
The Master device first performs a ‘dummy’ write operation
by sending the START condition, slave address and byte
address of the location it wishes to read. After the N24Cxx
acknowledges the byte address, the Master device resends
the START condition and the slave address, this time with
the R/W bit set to one. The N24Cxx then responds with its
acknowledge and sends the requested data byte. The Master
device does not acknowledge the data (NoACK) but will
generate a STOP condition (Figure 11).
Sequential Read
If during a Read session, the Master acknowledges the 1^st
data byte, then the N24Cxx will continue transmitting data
residing at subsequent locations until the Master responds
with a NoACK, followed by a STOP (Figure 12). In contrast
to Page Write, during Sequential Read the address count will
automatically increment to and then wrap−around at end of
memory (rather than end of page).
N
BUS ACTIVITY: ^S
O
T
S
A
SLAVE
AT
MASTER ^R ADDRESS
CO
T
KP
S
P
SLAVE
A
C
D ATA
K
BYTE
SCL
8
9
SDA
8^th Bit
DATA OUT
NO ACK
Figure 10. Immediate Read Sequence and Timing
BUS ACTIVITY: ^S
T
A
MASTER ^R
T
SLAVE
ADDRESS
ADDRESS
BYTE
S
T
A
SLAVE
R _ADDRESS
T
S
S
SLAVE
A
A
A
C
C
C
K
K
K
Figure 11. Selective Read Sequence
BUS ACTIVITY:
SLAVE
MASTER _ADDRESS
A
A
A
C
C
C
K
K
K
SLAVE
A
C
D ATA
K
BYTE
n
D ATA
BYTE
n+1
D ATA
BYTE
n+2
Figure 12. Sequential Read Sequence
STOP
N
O
S
AT
CO
KP
P
D ATA
BYTE
N
O
S
AT
CO
KP
P
D ATA
BYTE
n+x
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