N24C02 Datasheet, PDF (6/10 Pages) ON Semiconductor – 2-Kb, 4-Kb, 8-Kb and 16-Kb I2C CMOS Serial EEPROM

N24C02, N24C04, N24C08, N24C16
WRITE OPERATIONS
Byte Write
In Byte Write mode, the Master sends the START
condition and the Slave address with the R/W bit set to zero
to the Slave. After the Slave generates an acknowledge, the
Master sends the byte address that is to be written into the
address pointer of the N24Cxx. After receiving another
acknowledge from the Slave, the Master transmits the data
byte to be written into the addressed memory location. The
N24Cxx device will acknowledge the data byte and the
Master generates the STOP condition, at which time the
device begins its internal Write cycle to nonvolatile memory
(Figure 6). While this internal cycle is in progress (t_WR), the
SDA output will be tri−stated and the N24Cxx will not
respond to any request from the Master device (Figure 7).
Page Write
The N24Cxx writes up to 16 bytes of data in a single write
cycle, using the Page Write operation (Figure 8). The Page
Write operation is initiated in the same manner as the Byte
Write operation, however instead of terminating after the
data byte is transmitted, the Master is allowed to send up to
fifteen additional bytes. After each byte has been transmitted
the N24Cxx will respond with an acknowledge and
internally increments the four low order address bits. The
high order bits that define the page address remain
unchanged. If the Master transmits more than sixteen bytes
prior to sending the STOP condition, the address counter
‘wraps around’ to the beginning of page and previously
transmitted data will be overwritten. Once all sixteen bytes
are received and the STOP condition has been sent by the
Master, the internal Write cycle begins. At this point all
received data is written to the N24Cxx in a single write
cycle.
Acknowledge Polling
The acknowledge (ACK) polling routine can be used to
take advantage of the typical write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation, the N24Cxx initiates the internal write cycle. The
ACK polling can be initiated immediately. This involves
issuing the start condition followed by the slave address for
a write operation. If the N24Cxx is still busy with the write
operation, NoACK will be returned. If the N24Cxx has
completed the internal write operation, an ACK will be
returned and the host can then proceed with the next read or
write operation.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the operation of
the N24Cxx. The state of the WP pin is strobed on the last
falling edge of SCL immediately preceding the first data
byte (Figure 9). If the WP pin is HIGH during the strobe
interval, the N24Cxx will not acknowledge the data byte and
the Write request will be rejected.
Delivery State
The N24Cxx is shipped erased, i.e., all bytes are FFh.
BUS ACTIVITY: ^S
T
MASTER
A
SLAVE
R _ADDRESS
T
S
ADDRESS
BYTE
a₇ − a₀
DATA
BYTE
S
T
O
d₇ − d₀
P
P
SLAVE
A
A
A
C
C
C
K
K
K
Figure 6. Byte Write Sequence
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