N24C02 Datasheet, PDF (4/10 Pages) ON Semiconductor – 2-Kb, 4-Kb, 8-Kb and 16-Kb I2C CMOS Serial EEPROM

N24C02, N24C04, N24C08, N24C16
Power−On Reset (POR)
Each N24Cxx* incorporates Power−On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state.
A N24Cxx device will power up into Standby mode after
V_CC exceeds the POR trigger level and will power down into
Reset mode when V_CC drops below the POR trigger level.
This bi−directional POR feature protects the device against
‘brown−out’ failure following a temporary loss of power.
*For common features, the N24C02/04/08/16 will be
referred to as N24Cxx.
Pin Description
SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this pin
is open drain. Data is acquired on the positive edge, and is
delivered on the negative edge of SCL.
A0, A1 and A2: The Address inputs set the device address
when cascading multiple devices. When not driven, these
pins are pulled LOW internally.
WP: The Write Protect input pin inhibits all write
operations, when pulled HIGH. When not driven, this pin is
pulled LOW internally.
Functional Description
The N24Cxx supports the Inter−Integrated Circuit (I²C)
Bus data transmission protocol, which defines a device that
sends data to the bus as a transmitter and a device receiving
data as a receiver. Data flow is controlled by a Master device,
which generates the serial clock and all START and STOP
conditions. The N24Cxx acts as a Slave device. Master and
Slave alternate as either transmitter or receiver.
I²C Bus Protocol
The I²C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the V_CC supply via pull−up
resistors. Master and Slave devices connect to the 2−wire
bus via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see AC Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is high. An SDA transition while SCL is
high will be interpreted as a START or STOP condition
(Figure 2). The START condition precedes all commands. It
consists of a HIGH to LOW transition on SDA while SCL
is HIGH. The START acts as a ‘wake−up’ call to all
receivers. Absent a START, a Slave will not respond to
commands. The STOP condition completes all commands.
It consists of a LOW to HIGH transition on SDA while SCL
is HIGH.
NOTE: The I/O pins of N24Cxx do not obstruct the SCL and
SDA lines if the VCC supply is switched off. During
power−up, the SCL and SDA pins (connected with pull−up
resistors to VCC) will follow the VCC monotonically from
VSS (0 V) to nominal VCC value, regardless of pull−up
resistor value. The delta between the VCC and the
instantaneous voltage levels during power ramping will be
determined by the relation between bus time constant
(determined by pull−up resistance and bus capacitance) and
actual VCC ramp rate.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8−bit
serial Slave address. For normal Read/Write operations, the
first 4 bits of the Slave address are fixed at 1010 (Ah). The
next 3 bits are used as programmable address bits when
cascading multiple devices and/or as internal address bits.
The last bit of the slave address, R/W, specifies whether a
Read (1) or Write (0) operation is to be performed. The 3
address space extension bits are assigned as illustrated in
Figure 3. A₂, A₁ and A₀ must match the state of the external
address pins, and a₁₀, a₉ and a₈ are internal address bits.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA line
during the 9th clock cycle (Figure 4). The Slave will also
acknowledge the address byte and every data byte presented
in Write mode. In Read mode the Slave shifts out a data byte,
and then releases the SDA line during the 9^th clock cycle. As
long as the Master acknowledges the data, the Slave will
continue transmitting. The Master terminates the session by
not acknowledging the last data byte (NoACK) and by
issuing a STOP condition. Bus timing is illustrated in
Figure 5.
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