N24C02 Datasheet, PDF (3/10 Pages) ON Semiconductor – 2-Kb, 4-Kb, 8-Kb and 16-Kb I2C CMOS Serial EEPROM

N24C02, N24C04, N24C08, N24C16
Table 5. PIN IMPEDANCE CHARACTERISTICS
(V_CC = 1.7 V / 1.6 V* to 5.5 V, T_A = −40°C to +85°C and V_CC = 1.8 V to 5.5 V, T_A = −40°C to +125°C, unless otherwise specified.)
Symbol
Parameter
Conditions
Max
Units
C_IN (Note 4) SDA I/O Pin Capacitance
V_IN = 0 V
8
pF
C_IN (Note 4) Input Capacitance (other pins)
V_IN = 0 V
6
pF
I_WP, I_A
(Note 5)
WP Input Current, Address Input
Current (A0, A1, A2)
V_IN < V_IH, V_CC = 5.5 V
V_IN < V_IH, V_CC = 3.3 V
50
mA
35
V_IN < V_IH, V_CC = 1.7 V
25
V_IN > V_IH
2
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V_CC), the strong pull−down reverts to a weak current source.
*V_CC(min) = 1.6 V for Read operations, T_A = −20°C to +85°C.
Table 6. A.C. CHARACTERISTICS
(V_CC = 1.7 V / 1.6 V* to 5.5 V, T_A = −40°C to +85°C and V_CC = 1.8 V to 5.5 V, T_A = −40°C to +125°C, unless otherwise specified.) (Note 6)
Standard
Fast
Fast−Plus
Symbol
Parameter
Min
Max
Min
F_SCL
Clock Frequency
100
t_HD:STA
START Condition Hold Time
4
0.6
t_LOW
Low Period of SCL Clock
4.7
1.3
t_HIGH
High Period of SCL Clock
4
0.6
t_SU:STA
START Condition Setup Time
4.7
0.6
t_HD:DAT
Data In Hold Time
0
0
t_SU:DAT
Data In Setup Time
250
100
t_R (Note 7)
SDA and SCL Rise Time
1,000
t_F (Note 7)
SDA and SCL Fall Time
300
t_SU:STO
STOP Condition Setup Time
4
0.6
t_BUF
Bus Free Time Between
4.7
1.3
STOP and START
Max
400
300
300
Min
0.26
0.50
0.26
0.26
0
50
0.26
0.5
Max
1,000
120
120
Units
kHz
ms
ms
ms
ms
ms
ns
ns
ns
ms
ms
t_AA
SCL Low to Data Out Valid
3.5
0.9
0.45
ms
t_DH (Note 7) Data Out Hold Time
100
100
50
ns
T_i (Note 7)
Noise Pulse Filtered at SCL
50
50
and SDA Inputs
50
ns
t_SU:WP
WP Setup Time
0
0
0
t_HD:WP
WP Hold Time
2.5
2.5
1
t_WR
Write Cycle Time
4
4
t_PU (Notes 7, 8) Power-up to Ready Mode
0.35
0.35
6. Test conditions according to “A.C. Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. t_PU is the delay between the time V_CC is stable and the device is ready to accept commands.
*V_CC(min) = 1.6 V for Read operations, T_A = −20°C to +85°C.
ms
ms
4
ms
0.35
ms
Table 7. A.C. TEST CONDITIONS
Input Levels
0.2 x V_CC to 0.8 x V_CC for V_CC ≥ 2.2 V
0.15 x V_CC to 0.85 x V_CC for V_CC < 2.2 V
Input Rise and Fall Times
≤ 50 ns
Input Reference Levels
Output Reference Levels
Output Load
0.3 x V_CC, 0.7 x V_CC
0.3 x V_CC, 0.7 x V_CC
Current Source: I_OL = 6 mA (V_CC ≥ 2.2 V); I_OL = 2 mA (V_CC < 2.2 V); C_L = 100 pF
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