N01S830HA Datasheet, PDF (8/13 Pages) ON Semiconductor – 1 Mb Ultra-Low Power Serial SRAM

N01S830HA, N01S830BA
CS
SCK
0123
SIO[3:0]
Instruction Mode Bits
C1 C0 H L
Notes: C[1:0] = 05h
MSB
Figure 11. QUAD Read Mode Register Sequence (RDMR)
Write Mode Register (WRMR)
This instruction provides the ability to write the mode
register. The Write Mode Register operation is executed by
driving CS low, then sending the WRMR instruction to the
CS
device. Immediately after the instruction, the data is driven
to the device on the SO (SIO0-3) pin(s). To complete the
operation, drive CS high to terminate the register write.
SCK
SI
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
Mode Register Data In
0000000176543210
SO
High−Z
Figure 12. SPI Write Mode Register Sequence
CS
SCK
SIO[1:0]
01234567
Instruction
Mode Bits
C3 C2 C1 C0 H H L L
Notes: C[3:0] = 01h
MSB
Figure 13. DUAL Write Mode Register Sequence
CS
SCK
0123
SIO[3:0]
Instruction Mode Bits
C1 C0 H L
Notes: C[1:0] = 01h
MSB
Figure 14. QUAD Write Mode Register Sequence
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