N01S830HA Datasheet, PDF (4/13 Pages) ON Semiconductor – 1 Mb Ultra-Low Power Serial SRAM

N01S830HA, N01S830BA
DEVICE OPERATIONS
Read Operation
The serial SRAM Read operation is started by by enabling
CS low. First, the 8-bit Read instruction is transmitted to the
device through the SI (or SIO0-3) pin(s) followed by the
24-bit address with the 7 MSBs of the address being “don’t
care” bits and ignored. In SPI mode, after the READ
instruction and address bits are sent, the data stored at that
address in memory is shifted out on the SO pin after the
output valid time. Additional “dummy” clock cycles (four in
DUAL and two in QUAD) are required to follow the
instruction and address inputs prior to the data being driven
out on the SIO0-3 pins while operating in these two modes.
CS
By continuing to provide clock cycles to the device, data
can continue to be read out of the memory array in
sequentially. The internal address pointer is automatically
incremented to the next higher address after each byte of
data is read out until the highest memory address is reached.
When the highest memory address is reached, 1FFFFh, the
address pointer wraps to the address 00000h. This allows the
read cycles to be continued indefinitely. All Read operations
are terminated by pulling CS high.
SCK _{0 1 2 3 4 5 6 7 8 9 10 11}
29 30 31 32 33 34 35 36 37 38 39
Instruction
24−bit address
SI 0 0 0 0 0 0 1 1 23 22 21 20 2 1 0
SO
High−Z
Data Out
76543210
Figure 2. SPI Read Sequence (Single Byte)
CS
SCK _{0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39}
Instruction
24−bit address
SI 0 0 0 0 0 0 1 1 23 22 21 20 2 1 0
Don’t Care
ADDR 1
Data Out from ADDR 1
SO
High−Z
76543210
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Don’t Care
Data Out from ADDR 2
Data Out from ADDR 3
Data Out from ADDR n
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 ... 7 6 5 4 3 2 1 0
Figure 3. SPI Read Sequence (Sequential Bytes)
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