MC74HC589A_05 Datasheet, PDF (8/14 Pages) ON Semiconductor – 8-Bit Serial or Parallel-Input/Serial-Output Shift Register with 3-State Output High−Performance Silicon−Gate CMOS

A−H
LATCH
CLOCK
DATA
VALID
50%
t_su
t_h
50%
Figure 7.
MC74HC589A
Switching Waveforms
V_CC
S_A
GND
SHIFT
CLOCK
DATA
VALID
50%
t_su
t_h
50%
Figure 8.
V_CC
GND
SERIAL SHIFT/
PARALLEL
LOAD
SHIFT
CLOCK
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
C_L*
50%
t_su
50%
V_CC
GND
Figure 9.
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 kW
C_L*
CONNECT TO V_CC WHEN
TESTING t_PLZ AND t_PZL.
CONNECT TO GND WHEN
TESTING t_PHZ AND t_PZH.
*Includes all probe and jig capacitance.
Figure 10. Test Circuit
*Includes all probe and jig capacitance.
Figure 11. Test Circuit
Pin Descriptions
Data Inputs
A, B, C, D, E, F, G, H (Pins 15, 1, 2, 3, 4, 5, 6, 7)
Parallel data inputs. Data on these inputs are stored in the
data latch on the rising edge of the Latch Clock input.
S_A (Pin 14)
Serial data input. Data on this input is shifted into the shift
register on the rising edge of the Shift Clock input if Serial
Shift/Parallel Load is high. Data on this input is ignored
when Serial Shift/Parallel Load is low.
Control Inputs
Serial Shift/Parallel Load (Pin 13)
Shift register mode control. When a high level is applied
to this pin, the shift register is allowed to serially shift data.
When a low level is applied to this pin, the shift register
accepts parallel data from the data latch.
Shift Clock (Pin 11)
Serial shift clock. A low−to−high transition on this input
shifts data on the serial data input into the shift register and
data in stage H is shifted out Q_H, being replaced by the data
previously stored in stage G.
Latch Clock (Pin 12)
Data latch clock. A low−to−high transition on this input
loads the parallel data on inputs A−H into the data latch.
Output Enable (Pin 10)
Active−low output enable A high level applied to this pin
forces the Q_H output into the high impedance state. A low
level enables the output. This control does not affect the state
of the input latch or the shift register.
Output
Q_H (Pin 9)
Serial data output. This pin is the output from the last stage
of the shift register. This is a 3−state output.
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