MC74HC589A_05 Datasheet, PDF (6/14 Pages) ON Semiconductor – 8-Bit Serial or Parallel-Input/Serial-Output Shift Register with 3-State Output High−Performance Silicon−Gate CMOS

MC74HC589A
TIMING REQUIREMENTS (Input t_r = t_f = 6 ns, Note 10)
V_CC
Guaranteed Limit
Symbol
Parameter
V *55_C to 25_C v85_C v125_C Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ t_su
Minimum Setup Time, A−H to Latch Clock
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{(Figure 7)}
2.0
100
3.0
40
4.5
20
6.0
17
125
150
ns
50
60
25
30
21
26
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tsu
Minimum Setup Time, Serial Data Input S_A to Shift Clock
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{(Figure 8)}
2.0
100
3.0
40
4.5
20
6.0
17
125
150
ns
50
60
25
30
21
26
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tsu
Minimum Setup Time, Serial Shift/Parallel Load to Shift Clock
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{(Figure 9)}
2.0
100
3.0
40
4.5
20
6.0
17
125
150
ns
50
60
25
30
21
26
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _th
Minimum Hold Time, Latch Clock to A−H
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{(Figure 7)}
2.0
25
3.0
10
4.5
5
6.0
5
30
40
ns
12
15
6
8
6
7
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ t_h
Minimum Hold Time, Shift Clock to Serial Data Input S_A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{(Figure 8)}
2.0
5
3.0
5
4.5
5
6.0
5
5
5
ns
5
5
5
5
5
5
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tw
Minimum Pulse Width, Shift Clock
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{(Figure 4)}
2.0
75
3.0
40
4.5
15
6.0
13
95
110
ns
50
60
19
23
16
19
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tw
Minimum Pulse Width, Latch Clock
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{(Figure 3)}
2.0
80
3.0
40
4.5
16
6.0
14
100
120
ns
50
60
20
24
17
20
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tw
Minimum Pulse Width, Serial Shift/Parallel Load
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{(Figure 6)}
2.0
80
3.0
40
4.5
16
6.0
14
100
120
ns
50
60
20
24
17
20
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ t_r, t_f
Maximum Input Rise and Fall Times
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{(Figure 3)}
2.0
1000
3.0
800
4.5
500
6.0
400
1000
1000
ns
800
800
500
500
400
400
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{10.Information on typical parametric values can be found in the ON Semiconductor High−Speed CMOS Data Book (DL129/D).}
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