MC74HC589A_05 Datasheet, PDF (5/14 Pages) ON Semiconductor – 8-Bit Serial or Parallel-Input/Serial-Output Shift Register with 3-State Output High−Performance Silicon−Gate CMOS

MC74HC589A
AC ELECTRICAL CHARACTERISTICS (C_L = 50 pF, Input t_r = t_f = 6 ns, Notes 8 and 9)
V_CC
Guaranteed Limit
Symbol
Parameter
V *55_C to 25_C v85_C v125_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ f_max
Maximum Clock Frequency (50% Duty Cycle)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{(Figures 4 and10)}
2.0
6.0
3.0
15
4.5
30
6.0
35
4.8
4.0
10
8.0
24
20
28
24
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^tPHL
Maximum Propagation Delay, Latch Clock to Q_H
(Figures 3 and 10)
2.0
175
3.0
100
4.5
40
6.0
30
225
275
110
125
50
60
40
50
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^tPHL
Maximum Propagation Delay, Shift Clock to Q_H
(Figures 4 and 10)
2.0
160
3.0
90
4.5
30
6.0
25
200
240
130
160
40
48
30
40
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^tPHL
Maximum Propagation Delay, Serial Shift/Parallel Load to Q_H
(Figures 6 and 10)
2.0
160
3.0
90
4.5
30
6.0
25
200
240
130
160
40
48
30
40
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ t_PLZ,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^tPHZ
Maximum Propagation Delay, Output Enable to Q_H
(Figures 5 and 11)
2.0
150
3.0
80
4.5
27
6.0
23
170
200
100
130
30
40
25
30
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tPZL,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^tPZH
Maximum Propagation Delay, Output Enable to Q_H
(Figures 5 and 11)
2.0
150
3.0
80
4.5
27
6.0
23
170
200
100
130
30
40
25
30
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tTLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^tTHL
Maximum Output Transition Time, Any Output
(Figures 3 and 10)
2.0
60
3.0
23
4.5
12
6.0
10
75
90
27
31
15
18
13
15
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Cin
Maximum Input Capacitance
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Cout
Maximum Three−State Output Capacitance
(Output in High−Impedance State)
−
10
−
15
10
10
15
15
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{8. For propagation delays with loads other than 50 pF, see the ON Semiconductor High−Speed CMOS Data Book (DL129/D).}
Unit
MHz
ns
ns
ns
ns
ns
ns
pF
pF
9. Information on typical parametric values can be found in the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25_C, V_CC = 5.0 V
C_PD
Power Dissipation Capacitance (per Package)*
50
pF
*Used to determine the no−load dynamic power consumption: P_D = C_PD V_CC2f + I_CC V_CC. For load considerations, see the ON Semiconductor
High−Speed CMOS Data Book (DL129/D).
http://onsemi.com
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