CAT5221_13 Datasheet, PDF (8/15 Pages) ON Semiconductor – Dual Digital Potentiometer (POT)

CAT5221
CAT5221 initiates the internal write cycle. ACK polling can
be initiated immediately. This involves issuing the start
condition followed by the slave address. If the CAT5221 is
still busy with the write operation, no ACK will be returned.
If the CAT5221 has completed the write operation, an ACK
will be returned and the host can then proceed with the next
instruction operation.
CAT5221 0 1 0 1 A3 A2 A1 A0
* A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.
** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.
Figure 6. Slave Address Bits
SLAVE
ADDRESS
INSTRUCTION
BYTE
S
T
BUS ACTIVITY:
MASTER
A
R
T
SDA LINE S
S
T
DR WCR DATA
O
P
P
A
A
A
C
C
C
K
K
K
Figure 7. Write Timing
INSTRUCTIONS AND REGISTER DESCRIPTION
Instructions
Slave Address Byte
The first byte sent to the CAT5221 from the master/
processor is called the Slave Address Byte. The most
significant four bits of the slave address are a device type
identifier. These bits for the CAT5221 are fixed at 0101[B]
(refer to Figure 8).
The next four bits, A3 − A0, are the internal slave address
and must match the physical device address which is defined
by the state of the A3 − A0 input pins for the CAT5221 to
successfully continue the command sequence. Only the
device which slave address matches the incoming device
address sent by the master executes the instruction. The A3
− A0 inputs can be actively driven by CMOS input signals
or tied to V_CC or V_SS.
Device Type
Identifier
Instruction Byte
The next byte sent to the CAT5221 contains the
instruction and register pointer information. The four most
significant bits used provide the instruction opcode I [3:0].
The P0 bit points to one of the Wiper Control Registers. The
least two significant bits, R1 and R0, point to one of the four
data registers of each associated potentiometer. The format
is shown in Figure 9.
Table 11. DATA REGISTER SELECTION
Data Register Selected
R1
R0
DR0
0
0
DR1
0
1
DR2
1
0
DR3
1
1
Slave Address
ID3
0
(MSB)
I3
(MSB)
ID2
ID1
ID0
A3
A2
1
0
1
Figure 8. Identification Byte Format
Instruction
Opcode
WCR/Pot Selection
I2
I1
I0
0
P0
Figure 9. Instruction Byte Format
A1
A0
(LSB)
Data Register
Selection
R1
R0
(LSB)
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