CAT5221_13 Datasheet, PDF (5/15 Pages) ON Semiconductor – Dual Digital Potentiometer (POT)

CAT5221
Table 5. D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Test Conditions
Min
Typ
Max
I_CC
I_SB
I_LI
I_LO
V_IL
V_IH
V_OL1
Power Supply Current
Standby Current (V_CC = 5.0 V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (V_CC = 3.0 V)
f_SCL = 400 kHz
V_IN = GND or V_CC; SDA Open
V_IN = GND to V_CC
V_OUT = GND to V_CC
I_OL = 3 mA
−1
V_CC x 0.7
1
1
10
10
V_CC x 0.3
V_CC + 1.0
0.4
Units
mA
mA
mA
mA
V
V
V
Table 6. CAPACITANCE (T_A = 25C, f = 1.0 MHz, V_CC = 5 V)
Symbol
Parameter
C_I/O (Note 8)
C_IN (Note 8)
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, A3, SCL)
Test Conditions
V_I/O = 0 V
V_IN = 0 V
Min
Typ
Max
Units
8
pF
6
pF
Table 7. A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Min
Typ
Max
Units
f_SCL
Clock Frequency
T_I (Note 8) Noise Suppression Time Constant at SCL, SDA Inputs
t_AA
SLC Low to SDA Data Out and ACK Out
t_BUF (Note 8) Time the Bus Must Be Free Before a New Transmission Can Start
1.2
t_HD:STA
Start Condition Hold Time
0.6
t_LOW
Clock Low Period
1.2
t_HIGH
Clock High Period
0.6
t_SU:STA
Start Condition Setup Time (For a Repeated Start Condition)
0.6
t_HD:DAT
Data in Hold Time
0
t_SU:DAT
Data in Setup Time
100
t_R (Note 8) SDA and SCL Rise Time
t_F (Note 8) SDA and SCL Fall Time
t_SU:STO
Stop Condition Setup Time
0.6
t_DH
Data Out Hold Time
50
400
kHz
50
ns
0.9
ms
ms
ms
ms
ms
ms
ns
ns
0.3
ms
300
ns
ms
ns
Table 8. POWER UP TIMING (Note 8) (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Min
Typ
Max
Units
t_PUR
Power-up to Read Operation
t_PUW
Power-up to Write Operation
8. This parameter is tested initially and after a design or process change that affects the parameter.
1
ms
1
ms
Table 9. WRITE CYCLE LIMITS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Min
Typ
Max
Units
t_WR
Write Cycle Time
5
ms
NOTE: The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
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